Module instantiation in verilog

[gauravmp]

Hi,

I'm trying to move variables from one module to another to make the code look nice. The code that I'm working is a little too complex so I copied a piece of simple code from online to test if this would work. Specifically, what I'm trying to achieve is to be able to input data from the top module into the lower modules and receive data back from the lower modules to the top module after some computation. However, when I do a simulation, it looks like the data doesn't move. Could some one please help me out?

My top module is this:

module file_top (
result        , // Output of the adder
carry         , // Carry output of adder
r1            , // first input
r2            , // second input
ci              // carry input
);
   
input    [3:0]   r1         ;
input    [3:0]   r2         ;
input            ci         ;


output   [3:0]  result      ;
output          carry       ;


wire     [3:0]    r1        ;
wire     [3:0]    r2        ;
wire              ci        ;
wire     [3:0]    result    ;
wire              carry     ;


wire              c1        ;
wire              c2        ;
wire              c3        ;

file_1 u0 (
.a           (r1[0])        ,
.b           (r2[0])        ,
.ci          (ci)           ,
.sum         (result[0])    ,
.co          (c1)
);

file_1 u1 (
.a           (r1[1])        ,
.b           (r2[1])        ,
.ci          (c1)           ,
.sum         (result[1])    ,
.co          (c2)
);

file_1 u2 (
.a           (r1[2])        ,
.b           (r2[2])        ,
.ci          (c2)           ,
.sum         (result[2])    ,
.co          (c3)
);

file_1 u3 (
.a           (r1[3])        ,
.b           (r2[3])        ,
.ci          (c3)           ,
.sum         (result[3])    ,
.co          (carry)
);

endmodule



My bottom module is:


module file_1(
    a,
    b,
    ci,
    sum,
    co
    );

input a,b,ci;
output sum,co;

wire a,b,c;
wire sum,co;

assign {co,sum} = a + b + ci;

endmodule



My testbench is:

module file_tb(

    );
   
reg[3:0] r1,r2;
reg ci;
wire[3:0] result;
wire carry;
   
file_top inst1(
.result(result),
.carry(carry),
.r1(r1),
.r2(r2),
.ci(ci)
);

initial
begin
r1 = 4; r2 = 3;
#50
r1 = 2; r2 = 7;
#50
r1 = 3;r2 = 7;
end

endmodule



And the sim I get is attached here. ANy help would be very much appreciated.

[Sal Ammoniac]

ci is an input to your module file_1, yet you're not setting it to anything in your test bench.

[gauravmp]

Thanks!! It works now. Do you know what might be the problem if I see a Z in the simulation? Does it mean that the register isn't connected to anything?

[Sal Ammoniac]

 

Thanks!! It works now.

Excellent. I'm glad I could share my vast FPGA knowledge with you. All two weeks worth. 

Most of the time when I see a 'Z' in a simulation output it's due to an output not being driven. Check your module connections.