The Applications section of the 68030 User Manual has information about replacing 020 with 030. They are not pin compatible, but that is the single biggest hurdle.
One thing that either makes this easier or much harder is the asynchronous bus of the 020. The 030 fully supports this async mode (its faster synchronous mode won't be used in this case, without hardware change). If the board designers did their job "right" and asserted the DTACK (Data Transfer ACKnowledge) signals with the appropriate delay in all cases, then increasing the CPU clock is of no consequence. However, if they simply assert DTACK immediately and then depend upon the inherent delay in the bus cycle timing to allow enough time for devices (RAM, ROM, whatever) to work correctly, then you will have issues. The increased CPU speed means that the bus cycle will go faster. If the DTACK delay is explicit, then the faster 030 may (or may not) simply need to wait a cycle or two for the bus cycle, and all is good. If the delay is implicit, then the faster 030 may read invalid data too early, or terminate a write cycle prematurely.
Note of course that without specific code support for the 030, the data cache will not be enabled, and therefore the performance benefit of it is not realized. This becomes even more important at a higher clock speed, as the 030 will need to wait longer (in cycles) for RAM access than the 020 needed to do. Fortunately, the 020 also has an instruction cache and I assume this should continue to work with the 030 (though I'd definitely compare the cache control registers to make sure!). Simply turning on the data cache isn't sufficient, as ALL bus accesses will be cached unless either: the hardware asserts the cache inhibit line during the bus access, or, the MMU is configured to mark a memory region as non-cacheable. One or the other must be done for (e.g.) all I/O accesses to hardware where the same memory addresses (devices registers) are read repeatedly to capture new data. If this memory is cached, you get old data from cache instead of new data from hardware.