MSP430 output rise time

[electrolust]

Is the output frequency spec the correct thing to look at when trying to determine what the rise time when setting an output high will be?  https://e2e.ti.com/support/microcontrollers/msp430/f/166/t/81249 seems to say it is.

For my device, G2121, that spec is 12MHz @ 3V, R=1k, C=20p.  By the bandwidth/rt relationship: .35/.012 = 29ns.  Does that seem about right?

The max clock frequency at 3V is maybe 14MHz, so I take it that 12MHz reflects the rise time limitation of the output itself and not the fastest rate at which the output can be toggled just due to clock speed limits.

I'll also note that 2.2RC = 44ns.  The calculated rt is actually faster than that!  But the 1k load is a resistive divider .5k/.5k and Vo is the center tap.  I don't understand how that center tap ever gets to .9*VCC (shouldn't it only get to half of that? maybe the spec is misdocumented and that's what they mean) but anyway if we use .5k as R then 2.2RC = 22ns, which seems to make a little more sense than 44ns.

Now, IIUC, if I reduce RC, I'm not going to reduce the rise time of the output because I'm already below the limit.  Yes?

[amspire]

Is the output frequency spec the correct thing to look at when trying to determine what the rise time when setting an output high will be?  https://e2e.ti.com/support/microcontrollers/msp430/f/166/t/81249 seems to say it is.

For my device, G2121, that spec is 12MHz @ 3V, R=1k, C=20p.  By the bandwidth/rt relationship: .35/.012 = 29ns.  Does that seem about right?

The max clock frequency at 3V is maybe 14MHz, so I take it that 12MHz reflects the rise time limitation of the output itself and not the fastest rate at which the output can be toggled just due to clock speed limits.


I'll also note that 2.2RC = 44ns.  The calculated rt is actually faster than that!  But the 1k load is a resistive divider .5k/.5k and Vo is the center tap.  I don't understand how that center tap ever gets to .9*VCC (shouldn't it only get to half of that? maybe the spec is misdocumented and that's what they mean) but anyway if we use .5k as R then 2.2RC = 22ns, which seems to make a little more sense than 44ns.

Now, IIUC, if I reduce RC, I'm not going to reduce the rise time of the output because I'm already below the limit.  Yes?

I haven't used these chips but the rise time will probably be under 10ns. If the circuit the pin is connected to has a 100pF capacitance, the risetime may rise to 20ns. Don't really know without testing it.

The speed of the chip will be set by internal design considerations, such as the longest chain of internal combinatorial logic has to be able to settle within one clock cycle. Also this chip is designed for sub mA operation - that is a major limit to the clock speed. You cannot guess anything concerning the outputs from the clock speed.

That post you referred to was one of the most use answers I have seen. He could have reduced it to "things get affected by things". He should have said "I do not know".

Someone who knows the chip will know that the output pins have an ON channel resistance - maybe 40 or 100 ohms. If the output connects to one or two part nearby, then that might be a 30pF capacitance. The time constant then for 40 ohms would be under 2ns. If you add a 1K load, it just acts as a resistive divider with the output resistance. So if the output is 40 ohms and it pulls high, then you get Vcc x 1K/(1K + 40) on the output.

Edit: not sure what to make of the output spec you attached. If it can get to 90% with a 1K load, then the port resistance is typically under 100ohms.  If you increase the load capacitance from say 20pf to 40pf, that should only slow the port by perhaps 2ns extra. If that is the best output specs published in the datasheet, it is very dissapointing since you you cannot base a design off typical specs anyway. you need to know the limits over the temperature range. 

That output spec is totally contradictory since they say the test is done at a 1K load and they also say it is done with 0.5k resistors to the two supply rails which is a 0.5K ohm load, and it implies the port resistance is less then 50 ohms.

[amspire]

I just dug up the data sheet - I hope this is the one:

http://www.ti.com/lit/ds/symlink/msp430g2121.pdf

At 3V supply, the output at 6mA drops typically 0.3V. That means the outputs at 3V supply are typically 50 ohms. At lower supply voltages, they will be higher.

Comparing this data sheet to other 430 data sheets, the 20pf/1k test is usually done with 2K resistors going to each supply, so it seems this data sheet has a misprint in talking about 2 x 0.5K resistors.

It is a very dissapointing data sheet. If there were minimum and maximum specifications, you could work out the worst case behaviour of the output ports across all devices.

[electrolust]

I did a quick test.  I used a single resistor and probed at the output pin.  The resistor is the only thing there (with longish cables) and the probe itself - 10pF.

VCC=3.3V

100r 2.65V 13.8ns   -- too much voltage drop so this isn't a useful number, but 100r is interesting to note
500r 3.14V 15.8ns
1k   3.22V 15.8ns
10k  3.26V 16.4ns
100k 3.26V 16.4ns

So this is certainly a lot better than the 29ms I thought the 12MHz number implied.  Can I use the voltage drop to imply the source resistance?  And use the source+load resistance to determine capacitance?  (1/2.2R)

For the 1k test, there's a 160mV drop.  That would be 24r84 source resistance.  But for 10k, it comes to 122r7.  (24.84+10k would be 3.29V vs measured 3.26V, limits of measurement maybe?)  That's half an order of magnitude so it seems like a significant error.

If we go with 24r8+1k as the total resistance, C = 15.8ns/2.2R = 7pF.

So that all seems reasonable, yes?

[amspire]

How have you got the 1K connected? Is it to ground and you are pulling the output high? Then the resistance is 50 ohms for a 0.16v drop.

The output rise time is not totally due to the output capacitance. The circuit driving the output mosfets will have a signifigant risetime driving the capacitances of the gates of the output mosfets.

What you can say is that if you add another 20pF load in the circuit, the increase in risetime will only be a few nanoseconds.

The other issue with the lame datasheet is that these properties can change with temperature. If you went down to 0 deg C, the resistance could be 25% less. If the chip went to 100 deg C, the resistance could reach double. If you need to run close to the limits, warm the cpu in the oven and try again to see if it much slower.

[rsjsouza]

It is a very dissapointing data sheet. If there were minimum and maximum specifications, you could work out the worst case behaviour of the output ports across all devices.

I usually find safer to use typical values instead of the "bleeding edge", as they should be guaranteed across the entire operating range - don't assume anything faster or slower. The fact electrolust got faster rise times is probably closer to 25°C than to 70°C.

[amspire]

I usually find safer to use typical values instead of the "bleeding edge", as they should be guaranteed across the entire operating range - don't assume anything faster or slower. The fact electrolust got faster rise times is probably closer to 25°C than to 70°C.

That is not what "typical" means. Typical means you could get a device that is faster or slower. It is not a guaranty of anything.

[electrolust]

How have you got the 1K connected? Is it to ground and you are pulling the output high? Then the resistance is 50 ohms for a 0.16v drop.

It is to ground.  Not sure what you mean about pulling the output high.  I mean, sure, I'm toggling the output high in the MCU.  But I don't have a pullup resistor going to VCC.  I mean, that wouldn't make sense for an output pin, right?  [Keep in mind I usually post in beginners section.]

VCC -> R1 (source) <-Vout-> R2 (1k) -> GND

Vout = R2 / (R1 + R2) * VCC = 3.22V; solving for R1 is ~25r.

The output rise time is not totally due to the output capacitance. The circuit driving the output mosfets will have a signifigant risetime driving the capacitances of the gates of the output mosfets.

ah.

What you can say is that if you add another 20pF load in the circuit, the increase in risetime will only be a few nanoseconds.

That was going to be my next empirical test.  I have significant ringing in my trace though, so I want to clean that up first.  My ground lead now is just connecting another scope input ground to the PSU ground.  It's fairly horrible, just wanted to get it done super fast to see some kind of result.  I think the overshoot is causing the rise time to be overestimated.

The other issue with the lame datasheet is that these properties can change with temperature. If you went down to 0 deg C, the resistance could be 25% less. If the chip went to 100 deg C, the resistance could reach double. If you need to run close to the limits, warm the cpu in the oven and try again to see if it much slower.

Another thing I noticed on the spec sheet is that the voltage drop curve is not linear, meaning the internal source resistance is changing with total current (probably both per-pin and overall, although the spec only shows the effect of a single pin).  I suppose that is the nature of the output mosfet.  That would explain why I don't see a linear drop as I change the load resistor.  I'll try a careful evaluation after I fix the ringing.

[amspire]

How have you got the 1K connected? Is it to ground and you are pulling the output high? Then the resistance is 50 ohms for a 0.16v drop.

It is to ground.  Not sure what you mean about pulling the output high.  I mean, sure, I'm toggling the output high in the MCU.  But I don't have a pullup resistor going to VCC.  I mean, that wouldn't make sense for an output pin, right?  [Keep in mind I usually post in beginners section.]

VCC -> R1 (source) <-Vout-> R2 (1k) -> GND

Vout = R2 / (R1 + R2) * VCC = 3.22V; solving for R1 is ~25r.

The method used in the datasheet to test the output is to use a2k resistor from the output to the 3.3V, and another 2K from the output to 0V. The two resistors together make a 1K resistance connected to 3.3/2V. This way they can test that the output con both pull up to 3.3V and down to 0V. The way you have it connected, you cannot see if the output can pull to 0V as the resistor is pulling to 0V anyway.

Your way is totally fine in a practical circuit, but not so good for testing.

...

Another thing I noticed on the spec sheet is that the voltage drop curve is not linear, meaning the internal source resistance is changing with total current (probably both per-pin and overall, although the spec only shows the effect of a single pin).  I suppose that is the nature of the output mosfet.  That would explain why I don't see a linear drop as I change the load resistor.  I'll try a careful evaluation after I fix the ringing.

The ringing is almost certainly the scope probe and the ground lead. Make sure the ground lead is connected to each scope probe and clip the ground as close as you can to the processor chip. Just know that as long as your board has a good number of ceramic capacitors filtering the supply near the chips, it will be fine. Do not worry too much about the ringing on the scope.

[electrolust]

How have you got the 1K connected? Is it to ground and you are pulling the output high? Then the resistance is 50 ohms for a 0.16v drop.

VCC -> R1 (source) <-Vout-> R2 (1k) -> GND

Vout = R2 / (R1 + R2) * VCC = 3.22V; solving for R1 is ~25r.

Indeed we are both right.  For .16v drop it would be 50r.  But the drop was only .08v.  When I said 160mV I was reading the .5k load test results not the 1k load test results.

[electrolust]

Can I use the voltage drop to imply the source resistance?  And use the source+load resistance to determine capacitance?  (1/2.2R)

I guess not.  The probe does not form a series RC filter.

Anyway, with 1k load, a 10M//11pF probe has 15.8ns rise time, and a 1M//3.5pF probe has 4.5ns risetime.

[electrolust]

I redid this.  First, I had the BW filter on earlier, so my rise times were wrong due to that.  I guess I thought it was a software filter but it turns out it isn't.  (duh, makes more sense to be a hw filter)

Also, my 3.5pF probe is actually 7pF.  I borrowed it though and wasn't able to retest that one.

I also obtained a Tek P6150 Z0 probe (they are cheap on ebay).  My new results are,

(10M // 9.5pF) // 1k load : 4.2ns
500r  // 0.15pF (no other load) : 3.8ns

Using the 10M probe I get the same results with loads of 500r all the way to 10M (effectively 5M seen by DUT, after considering the probe).  If I use the 1:1 tip on the P6150 (50r) the MCU output is loaded too heavily so this doesn't work correctly.

Is the 3.8ns a good estimate then of the best rise time I will ever get from this MCU output?

I've attached traces.  There is ringing on the 10M probe.  I'm curious why I see ringing on the one but not the other.  I'm using about the same length of leads on both probes, a few cm long from the probe tip to a breakout of the MCU pin.  (I'm not using the long ground clip thing on the 10M probe.)  So I kind of think it's not inductance from the leads.  Note that the ringing does not have an initial overshoot.

I also obtained an HP 10020A Z0 probe but I couldn't get good results with it.