Multi module systems communicate with data bus - VHDL

[dr.cnet]

Dear developer,
I am a newbie member here and would appreciate it if you guide me through this problem.
I am learning VHDL with a book titled: "Structured Logic Design with VHDL, J R. Armstrong" which I think its some kind of difficult for me to solve the problems by myself.
I couldn't solve this one and now need help.
Thanks.

PS: Question attached.