Author Topic: Multiple I2S masters MCLK issue.  (Read 885 times)

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Offline ee2000

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  • Country: dk
Multiple I2S masters MCLK issue.
« on: August 02, 2016, 03:06:12 am »
Hi

I am currently doing development on a audio board, where I have multiple I2S masters, which don't share a common oscillator,
as some off these sources are offboard audio signals S/PDIF (Multiple), all of the I2S master will be running 11.289600 Mhz (44.1kHz * 256).

The problem as I see it is that all the these I2S masters, even if they are running at the same clock speed (11.289600 Mhz), there will be drifting between
those oscillators, resulting in async signals between the masters giving an issue in the later processing stage.

The main processing unit is a FPGA I have been looking into resampling, but as i don't know if the individual clocks are faster/slower hence chosing up/downscaling selection, i am not sure how I should go about this issue ?

I hope some of you guy's are able to point me in the right direction.

Thanks a lot in advance.

regards
René




 

Online whollender

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Re: Multiple I2S masters MCLK issue.
« Reply #1 on: August 02, 2016, 04:24:48 am »
I think what you are looking for is called an "Asynchronous Sample Rate Converter".  It will take an input stream at a given sample rate, and resample it to another sample rate.  These are often used for the exact application you mention, where you have multiple data sources that all have the same nominal sample rate, but whose actual sample rates may drift with respect to one another, and you need to match everything to a master sample rate to do your processing.

I think that all the major players (TI, AD, Cirrus, etc) have ASRC chips.  You can also implement something in the FPGA to do the sample rate conversion; Xilinx even used to have some IP to do just that, but it isn't supported any longer.

They generally work by comparing the input and output sample rates to determine the resampling ratio, interpolating to a very high sample rate (practically continuous), and then decimating to the output sample rate.  Practically, poly-phase techniques and an FIR filter with reloadable coefficients are used to keep actual sample rates within reasonable limits.

All the audio work that I've done has been with a single master clock, so I haven't ever needed an ASRC, but the theory behind them is pretty fascinating.

If you don't want to dive into the theory, then you probably just want to drop in a couple of the ICs to get all of your inputs onto the same clock before processing.  You could implement something on the FPGA, but that would be a pretty involved project just by itself.
 

Offline ee2000

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  • Posts: 3
  • Country: dk
Re: Multiple I2S masters MCLK issue.
« Reply #2 on: December 08, 2016, 08:21:34 pm »
Hi

Sorry for the late reply, thanks a lot for you help and clarification of the issue I was facing

I found a link which explained the issue a bit more, and also some suggestion for IC that can handle the SRC:
https://ackspace.nl/wiki/Arbitrary_Sampling_Rate_Converter_in_VHDL 

Hope that is will help others :-)

regards
René
 


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