Multiple VHDL source files simulation with Active-HDL

[mn]

I am using Active-HDL to write VHDL codes. I am able to write ans simulate one file codes but when it comes to  multiple source files and components, the simulation doesn't work! It seems that there is a problem finding components in other source files. Please see the attached picture.


As you can see in the left pane, the test bench is selected as the top level. Any idea for that? the code is pretty simple and should work!

[ale500]

And you did add the file to the project, didn't you ?

[mn]

Yes. The workspace browser confirms that. Also, the compile all command actually compiles with the order. Please see the attachment.

[rstofer]

When you want to instantiate a separately compiled entity, you need to prefix the entity name with 'work.' as in

Inst_DMA : entity work.DMA PORT MAP (
...
);

Instantiation from one of my projects...

[mn]

Sorry, but got the same result! Please see the picture and source files. Thing is that ISE will run the simulation correctly. I don't know what is wrong with Active-HDL.

I have stuck at this problem. Any idea is welcomed.

[rstofer]

In your entity fa, remove the component ha and let the work.ha do the work.

I know absolutely NOTHING about ActiveHDL, I am taking my clues from an ISE project with over 20 externally compiled entities.  I have no idea what ActiveHDL expects.

[mn]

Same result... I am getting disappointed with Active-HDL. I also tried a simple NOT gate (one entity for the not and the other for port map) but the output doesn't change...

[deebee]

I tried your design and it works fine for me in activehdl, I changed the instantiations back to component rather than entity, i.e.

u1: fa port map( i1, i2, ci, s, co );

instead of

u1: entity work.fa port map( i1, i2, ci, s, co );

You have a component declaration so you don't need the second one, the second one is if you remove the component declaration

So there is nothing really wrong with your code. Not sure what else?

[mn]

Can you zip the workspace? Thanks in advance

[rstofer]

Declaring a component within an upper level architecture brings along a maintenance headache.  If the component changes, the changes need to be reflected twice in the upper level.  Once where the component is declared and again where it is instantiated.

It's simply a matter of style and, for the moment, I prefer work.xxx.  I could probably be talked out of it...

[deebee]

Zip of my workspace added, this was created with version 10.3 that comes with lattice diamond. Your screenshot seems to show version 10.1 so I don't know if it will load in directly.

As for declaring a component, most of the companies I have worked with do it this way, sometimes just because it is a long time standard practice (very important in the conservative ASIC world, we don't like to change what works, screwing things up gets very expensive  ), but I think more importantly is that instantiating with the entity syntax doesn't work well when using vhdl configurations. Configurations are often used on larger ASIC projects. For your own personal projects then whatever gets it done is fine really. Anyway VHDL is somewhat verbose and long winded at times so you just get used to the extra typing 

[mn]

It seems that there is a problem with the version 10.1 that I have.
Dear Deebee, please check your private messages.