Net Delays on Vivado after implementation

[gauravmp]

Hi,

I'm trying to find the delay through nets on Vivado after implementation but I'm not very sure where to find information about how to do this. Every time I look for something, I keep finding articles about ISE but I'm using Vivado 2016.. Can anyone familiar with finding net delays please let me know how to do this?

Any help would be appreciated.

Thanks,
Gaurav

[rstofer]

Well, this is going to tickle you!  Sorry, I really couldn't resist...

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_1/ug835-vivado-tcl-commands.pdf page 394

http://www.edaboard.com/thread364102.html

It looks like these TCL commands are intended to be run in a batch file and I haven't gotten far enough with Vivado to try that kind of thing.

[leavesw]

Try "Report Timing Summary" within "Open Implemented Design", you should be able to find your nets there and analyze the delay and placement there.