Nothing more than a memory

[jpanhalt]

That is fantastic thank you both very much.

Is it better to put variables into linear memory?

Better?  In what way?  As we have stated many times, Linear Memory IS GP RAM.   It's the same silicon, but mapped differently and accessed differently.  It's only advantage is that the entire GP RAM is mapped to contiguous space.   It is imaginary addresses, just like INDFn.  Since none of us have a clue what you need to do, we cannot answer that question in the abstract.  I am assuming you are new at this, and until you are comfortable using "pointers" (aka FSRn/INDFn registers), I will suggest not trying to use it.  Just use GP RAM or Common RAM as that you already know how to access.  By imaginary, you cannot watch it directly in a window.  If you want to know what is at a particular location (i.e., where the FSRn is pointing) you need to do a movf INDFn or moviw instruction.  For the moviw, read the datasheet.
 

Is flash program memory the same as program memory? Presumably this area is not used for variables or constants?

Same silicon, but again, accessed somewhat differently.   You set bit 7 of the FSRn you are using which acts as a flag to tell the assembler to access the program memory as data.  When (if) you use it, you will find that bit 7 is often set automatically; however, I suggest you do it in code at the start.  I use it for tables (i.e., constants).

I am assuming you are referring to use of program memory as described (i.e., all program memory in 16Fxxx chips is called "flash").   There is also memory specifically called flash program memory that operates much like EEPROM.

[Buriedcode]

Is it better to put variables into linear memory?

Well variables can only go in SRAM and for the most part, just use the cblock macro (it will assign memory locations sequentially).  I haven't used more modern 8-bitters with assembly so I am unsure of the memory structure of the RAM (banks).  I would have thought if you have a large array that crosses a boundary - the compiler will point this out to you.   A quick scan of the PIC16F1827 datasheet mentions the "linear data memory" you speak of, which appears to "allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.".

That just means when using the  FSR (file select register) can be incremented/decremented through-out the entire RAM without worrying about switching banks.

Side note: If you're unsure about using the FSR and INDF (indirect file register) then google indirect addressing - it is very handy for dealing with linear arrays and buffers.  Briefly, you put the address of the location you want to read/write to in the FSR, and that makes the INDF register the register it points to.  So for a linear array, you can simply increment/decrement the FSR to move up and down the array and read/write to the INDF register rather than deal with mnemonics.  It appears that the FSR covers both data and program memory, which can be confusing.

Is flash program memory the same as program memory? Presumably this area is not used for variables or constants?

Yup. To both questions.  These days as all program memory is flash, and they have provided the facility to self-write the flash, most PIC's can use a bootloader for programming. 

[jpanhalt]

Yup. To both questions.  These days as all program memory is flash, and they have provided the facility to self-write the flash, most PIC's can use a bootloader for programming.

It is actually a little more complicated than that, but the changes involve newer chips.  Of course, the program is flash, and that very same memory can be used for data and accessed indirectly with FSRn.  However, that memory cannot be written during run time.  It is from that perspective that I initially answered PerranOak.

However, I edited my comment on the chance that PerranOak had read the datasheet for newer PIC's (i.e, the 16F1827 he is using) and was wondering about another type of flash memory called HEF.(See my last sentence in previous post.) 

When the enhanced mid-range chips were introduced, e.g., 16F1516/7/8/9 family, Microchip introduced what it called at the time, High Endurance Flash memory (HEF flash).  That was memory in the program space that could be reprogrammed at run time just like EEPROM.   It seems the "HEF" term has been dropped, and the newest chips in the enhanced mid-range evolution include what is now called "Non Volatile Memory" (NVM, see 16F18856 for example).

I have the eval board for that chip, but have not used it yet.  Three things jump out based on a very brief review of its memory:
1) It appears Microchip has dropped HEF as an identifier and effectively combined EEPROM with it to give NVM.   They both (if that is still appropriate) use the same SFR registers to save and read the memory.
2) Write cycles have been increased greatly.
3) Access also can be by FSRn.  I have not studied the datasheet carefully enough to know whether FSRn can be used to write, but my guess it that it cannot do that.   Nevertheless, being able to read with FSRn will save bank switching.

[PerranOak]

Thank you again both.

Yes, I do seem to be struggling to get this into my brain! But I do have it now linear memory IS GP RAM!

I am assuming you are referring to use of program memory as described ...   There is also memory specifically called flash program memory that operates much like EEPROM.

This is what I was getting at. So, "flash program memory" and "program memory" are different: the former is like EEPROM and the latter is where the programme is stored?
It's true that I haven't used indirect addressing yet but I wanted to be sure that I would not over-write my programme when I did.

… the program is flash, and that very same memory can be used for data and accessed indirectly with FSRn.  However, that memory cannot be written during run time.

So, it's the "program memory" that can't be accessed during run time but the "flash program memory" can be, like EEPROM? I can't quite see the use of memory that can't be accessed during run time.
Is the "flash program memory" non-volatile?

My project is a thermometer that samples every second or hour or whatever and then stores the data. I am using EEPROM which is non-volatile but can only store 256 data points. This is why I was looking at other methods but got caught-up in my linear memory/GP RAM confusion too.

[JPortici]

When the enhanced mid-range chips were introduced, e.g., 16F1516/7/8/9 family, Microchip introduced what it called at the time, High Endurance Flash memory (HEF flash).  That was memory in the program space that could be reprogrammed at run time just like EEPROM.   It seems the "HEF" term has been dropped, and the newest chips in the enhanced mid-range evolution include what is now called "Non Volatile Memory" (NVM, see 16F18856 for example).

er.. no that's not correct.
first, in these pics flash memory CAN certainly be programmed during runtime, otherwise bootloaders wouldn't be possible.
In this aspect the difference between flash program memory and eeprom memory is that the core HALTS during flash memory erasing/programming, while it doesn't halt during eeprom erasing/programming.
Actually, in devices with dual panel flash/memory partitioning the core halts if it's performing erase/write in the active partition, while is doesn't if erase/write happens in the inactive partition.

The other two main differences between flash and eeprom are that flash is byte-erasable/writable, while flash is page-erasable and row-writable. you erase one whole page before being able to program one row (one row being N bytes, one page being M rows)
And the other is that the endurance of flash is significantly lower than eeprom. we are talking of 100-10k erase/write cycles for flash compared to > 1M erase/write cycles for EEPROM.
To mitigate this issue in lower cost devices with no eeprom (such as the PIC16F15xx series for example) the last page(s) of flash were so called "high endurance flash", which had an endurance in the order of 100k cycles, otherwise it is just flash, it's treated as such

** in the pic18 K42 series and probably others you can configure the last x pages of flash to be a data storage area, nothing fancy if not that the device resets if it attempts to execute the memory in that area

[jpanhalt]

The other two main differences between flash and eeprom are that flash is byte-erasable/writable, while flash is page-erasable and row-writable. you erase one whole page before being able to program one row (one row being N bytes, one page being M rows)
And the other is that the endurance of flash is significantly lower than eeprom. we are talking of 100-10k erase/write cycles for flash compared to > 1M erase/write cycles for EEPROM.

No, it is row erasable, not page of "M" rows.  I believe all chips are partial row writable, some can write a whole row.   The 16F1827 can do either.

It is important to understand the Flash program memory structure for erase and programming operations.
Flash Program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory
words. A row is the minimum block size that can be erased by user software.
[snip]
After a row has been erased, the user can reprogram all or a portion of this row.

The rows in that device are 32, 14-bit words long.  Since that device has 32 write latches, it can write a whole row, not not all devices have that many data latches.

I also ignored using a bootloader, as that would further cloud the issue.

It appears the OP's questions have been answered.