NXP RT1020 Program/Debug by SWD

[luiHS]

 
I also made this small JTAG adapter for my Jlink, to program the board I made with the RT1020, either with a 2x5-pin IDC connector by JTAG or a 5-pin connector by SWD.

The IDC connector of 2x5 is not the mini version of 1.27 mm, but a 2.54 mm, it may be replaced by the mini version for the final product.

[luiHS]

As for the connector, I much prefer the Tag-Connect system. No need to actually fit a connector even when debugging and the PCB footprint is tiny.

I have replaced on my board, the IDC JTAG and SWD connectors of 2.54 mm, for a TC2050 Tag-Connect, and I have ordered the cable and the adapter for Jlink to Digikey. I hope it's as good as it looks, and I'll use it in all my designs, the idea is good to save assembly time and some cost.

https://www.digikey.es/product-detail/es/tag-connect-llc/TC2050-ARM2010/TC2050-ARM2010-ND/3528170
https://www.digikey.es/product-detail/es/TC2050-IDC/TC2050-IDC-ND/2605366/?itemSeq=269348220

[MT]

There are ground planes in both layers, I do not think there are any problems with the GND.

If your PCB is 2 layer you dont have a GND plane rather GND "areas" as seen on your pictures. GND plane is when you dedicate an "entire layer" to GND. I have the same issues with my 2 layer board, spend lots of thinking how to route for low impedance/inductance. However most likely your board will work but will it be at optimum? you may/may not get funny things happening.

[luiHS]

There are ground planes in both layers, I do not think there are any problems with the GND.

If your PCB is 2 layer you dont have a GND plane rather GND "areas" as seen on your pictures. GND plane is when you dedicate an "entire layer" to GND. I have the same issues with my 2 layer board, spend lots of thinking how to route for low impedance/inductance. However most likely your board will work but will it be at optimum? you may/may not get funny things happening.

I understand what you mean, but making a 4-layer PCB is very expensive for my products. My main products have a big PCB, 380x130mm, 442x177mm and similar, these are special LED screens with HUB75 led modules. Converting these PCBs to 4 layers would greatly increase the cost of the product. Now all my boards with 2 layers work well with NXP Kinetis MK66, I hope they also work well with RT1020.

I always route manually and very carefully to avoid problems, and now with the RT1020, for the QSPI and the SDRAM, as they handle very fast signals, I will use the meander function of Eagle, to adjust the length of the tracks the same length. I also add vías to join both GND planes, avoiding bare copper areas on any of the faces.

I only had to make some designs to 4 layers, for clients that needed to pass the EMI emission certificate. One of those boards was made in the begining to 2 layers and did not pass the emission tests (picture attached), although almost, and I preferred to redo the board to 4 layers, as it was a small board did not increase the cost too much.

I trust that it can work well with 2-layer plates, in fact I think the NXP evaluation board for the RT1020, is made in 2 layers, or so I thought I read somewhere.

[luiHS]

 
Today I received the TC2050 cable from Digikey, and also the PCBs that I ordered from JLCPCB to make my first board with the NXP RT1020 LQFP100.

On the TC2050 cable, it's a bit short, I expected it to be a bit longer.

My board for the RT1020, has errors in the output ports that are handled with the DMA, because I was unaware that the pins must be from the same port and be contiguous. The same thing happened to me with the PCB I made for the RT1020 evaluation board. I have designed a small board that connects to the output of the IDC connector on my board, to reorder the ports, and there will be no problem.

I really want to start up this board, because I want to migrate several of my products with Kinetis MK66 as soon as possible. The details about the DMA, I am learning them little by little, and I think that I already have the necessary information to use the DMA by SPI in reception, and as an output to several GPIO ports from an array.

[luiHS]

Today I received my first PCB to use with TC2050 connector to Program/Debug by JTAG/SWD, and the look is really good. Everything fits perfectly, and in principle it seems a very good option to remove connectors on the board. I still have to try it, in this case with MCUXpresso to program a Kinetis MK66.

The plate for the RT1020 had already been ordered, before knowing this type of connectors, and it remains in the prototype for a standard IDC connector, but in the final product, I will also design to use the TC2050.

[luiHS]

Boards assembled, one with LQFP100 RT1020, and one to connect to the NXP evaluation board, so I can use the SDRAM until LQFP144 is available on December.

[dengzg]

Hi,
     I encounted with the same problem with Jlink V9. I had removed Jumper J27 & J28.
     I found that when connected Jlink V8 between host and target board and then power on target board, MCU could not be detected and when powered the board on first and then connected Jlink, MCU could be found correctly. Perhaps, some bugs with the power subsystem on target board.

[luiHS]

Hi,
     I encounted with the same problem with Jlink V9. I had removed Jumper J27 & J28.
     I found that when connected Jlink V8 between host and target board and then power on target board, MCU could not be detected and when powered the board on first and then connected Jlink, MCU could be found correctly. Perhaps, some bugs with the power subsystem on target board.

My boards with RT1020 and RT1050 work perfectly by JTAG, with Jlink V8 and V9, using MCUXpresso.