Opal Kelly FPGA boards, XEMxxxx series

[legacy]

so, Opal Kelly looks like a great company! When you look at their catalog their boards appear smart, small, and good, but then digging for the documentation reserves you a surprise since the design of their modules is proprietary, and if their "FrontPanel SDK" provides the user-facing interface for building applications, it's also true that I can't see any schematic, examples for the built-in Cypress-CY7C68013A used in the hyperlink USB part.

have you ever used their modules?

[Heartbreaker]

so, Opal Kelly looks like a great company! When you look at their catalog their boards appear smart, small, and good, but then digging for the documentation reserves you a surprise since the design of their modules is proprietary, and if their "FrontPanel SDK" provides the user-facing interface for building applications, it's also true that I can't see any schematic, examples for the built-in Cypress-CY7C68013A used in the hyperlink USB part.

have you ever used their modules?

Yes, I have used the XEM7310 recently and some time ago also the XEM6310 and the XEM3050. It is correct that the schematics and the remaining board documentation are not published. Although it is quite possible to use their SW API and Verilog/VHDL source to build an application with corresponding FPGA bit-stream.

I do not know which board you are targeting, but to use a current FPGA tool chain (Vivado) you need to move to 7th generation Xilinx silicon. Everything before that is Xilinx ISE which is starting to become (out)dated by todays standard. Vivado is the only tool that supports SystemVerilog and all the VHDL attributes for instance.

Normally I would not disclose the following kind of information, but I have given all this as feedback to OK and only parts of it has rippled trough to the documentation in due time.

Watch out for the NVRAM battery implementation. I haven't checked the XEM7310, but the XEM6130 had a flaw that they charged the battery to 50% of 3V3. According to the Seiko datasheet that is beyond 100% discharge. Furthermore the datasheet states that the battery only has a life of 100 cycles when utilized to 100% DoD (Depth of Discharge)!

Changing the signalling voltage in the Expansion Connector is as easy as removing FB1 and FB2 and supplying you own power to the power pins in the connector. The documentation mentions that there is a few pins exempted - which OK added after I pointed that one out for them. What they forgot to add is that the LEDs are also connected up to a bank used in the connector and they are running 3V3!

LEDs can only be used when running in a 3V3 environment otherwise they must be tied low to lit the LEDs. If used, the current from the 3V3 rail will flow through either the FPGA pin protection diodes or the P-FET to the power rail of that particular bank. If there is not enough load on that rail the rail will elevate and influence the input threshold level. It is a real pain to debug signal integrity problems inside ones FPGA because corners were cut during the implementation of the LEDs - trust me. OKs recommendation on how to drive the LEDs is simply a design no-go! You can't make a open-drain implementation that goes beyond the rail like that!

From their documentation XEM7310 looks like a plugin replacement for XEM6310, but look out for pin constraints particular which pins are powered from a fixed power rail. Try make a dummy project that utilizes all the pins. Vivado pin editor will highlight colliding constraints promptly.

Besides my rant above, I think they strive to do a good job and as a decent sized costumer of theirs, we have had quite good support from them. We all make mistakes and sometimes these are inherited to other platforms for compatibility reasons. I will use OK boards again in future projects.

/Sverre

Edit: Learning how to abbreviate OpalKelly

[legacy]

Although it is quite possible to use their SW API and Verilog/VHDL source to build an application with corresponding FPGA bit-stream

I need to interface the FPGA through USB with a PowerPC-rack machine running Linux-v4.18. The "USB-TPU" adapter need to be the smallest possible, and I need the source to compile the stuff on the HOST side.

I do not know which board you are targeting

the OpalKelly XEM6001 comes with exactly what I need:
- USB controller
- enough I/O pin
- enough BRAM in the FPGA

the FPGA is XC6SLX16

use a current FPGA tool chain (Vivado) you need to move to 7th generation Xilinx silicon. Everything before that is Xilinx ISE which is starting to become (out)dated by todays standard.

I am on ISE-{v10.1, v11.4, v14.7} on a Windows XP/32bit laptop.
I can't swap to Vivado/Windows10 at the moment. Probably in the near future I will, but not now.

I might consider Xilinx's tools on a x86-64bit/Linux 

Vivado is the only tool that supports SystemVerilog and all the VHDL attributes for instance.

I only use VHDL'2005, 'cause of my external tools, including my HDL simulator.

[Heartbreaker]

Although it is quite possible to use their SW API and Verilog/VHDL source to build an application with corresponding FPGA bit-stream

I need to interface the FPGA through USB with a PowerPC-rack machine running Linux-v4.18. The "USB-TPU" adapter need to be the smallest possible, and I need the source to compile the stuff on the HOST side.

I think you are out of luck, then. I do not recall that there is anything but x86 DLLs.

the OpalKelly XEM6001 is the smaller card, and it comes with exactly what I need:
- USB controller
- enough I/O pin
- enough BRAM in the FPGA

the FPGA is XC6SLX16

I am on ISE-{v10.1, v11.4, v14.7} on a Windows XP/32bit laptop.

Spartan-6 is ISE territory and matches your installation. I was going to suggest that ISE and Vivado could live together side by side, until I recalled that there are actually bindings to the OS as well. ISE is Win7 and earlier and Vivado is Win7 and beyond, but you are probably aware of that already.

[rstofer]

Spartan-6 is ISE territory and matches your installation. I was going to suggest that ISE and Vivado could live together side by side, until I recalled that there are actually bindings to the OS as well. ISE is Win7 and earlier and Vivado is Win7 and beyond, but you are probably aware of that already.

They can live side by side in Win 10.  I'm doing it.

I seem to recall a gotch' with the ISE installation.  Found it!
https://www.micro-nova.com/xilinx-ise-win10/