The AVR datasheet specifies "Read Low to Data Valid": 1.0tcl-50ns. At 16MHz this is only 12.5ns.
Compare this value with the "Output Enable to Output Valid" time in the SRAM datasheet. Most 55-80ns SRAMs will have a value of 25-50ns. Therefore it can work, but you may have reliability issues.
You should also use 74AC573 latches instead of 74HC573 for a better address setup time.
But AVRs can insert wait states: When using 1 wait state, the timing is fine for 70ns SRAMs.