The RT1020 will soon be available, according to representatives of NXP in its forums, on the 26th of this month. I am already preparing the design of the PCB for my own design, and although the Datasheet has not yet been published, nor the diagrams on the evaluation board, probably the external memory start system QSPI, Hyperflash or the SD card will be the same as in the RT1050.
I have the RT1050 evaluation board and the schematic of that board. It is the first time that I am going to design a PCB for such a fast microcotroller, until now I made designs with Cortex M4 at 168Mhz and 180Mhz and with Flash inside the microcontroller. The RT1020, is a Cortex M7 at 500Mhz, and has no flash, you have to put an external flash to boot, or use an SD card.
The issue in the design of the PCB, are the considerations of the tracks that go from the microcontroller to the Hyperflash memory and perhaps also to the QSPI memory. One user suggested that for the QSPI memory it would probably not need the "Lenght Tuning", in Eagle the "meander" function, to give the same length to the tracks of a bus.
As I'm not sure, I took some photos, from the evaluation board of the RT1050, this is somewhat faster, it goes to 600Mhz, and both the Hyperflash and the QSPI seem to have tracks tuned in length. I also took some pictures of the tracks of the SDRAM that it has, and the same, although this I will not put it in my design.
Any suggestions or advice to apply the "Lenght Tuning"? It is the first time I do it,I think it's not complicated, I will route everything by hand. I suppose that these tracks should go directly from the memory chips to the microcontroller, without using vĂas.
Here the Hyperflash memory on the TOP side.
The QSPI, on the TOP side, do not see any track with the length tuned.
The QSPI, for the BOTTON side, here there are some tuned tracks to same length
The board has an SDRAM, also with tuned tracks, on the TOP side.
The SDRAM, for the BOTTOM side.