pic 18f2550 config bits

[coromonadalix]

hello  i have a project who drives me mad

Im a noob in configuring the bit prior programming a pic 18f2550

It come from an open programmer project at : http://openprog.altervista.org/OP_eng.html

All files and mplab files are hosted and free, i want to build it to mostly interface dallas 24b33 1 wire eeproms.

The mplab file main.c  once open are showing this config bits (picture included) : 00 05 1F 1F 00 83 85 00 0F C0 0F E0 0F 40                       

The adresses at 300004, 300007 are 00 values ??  i'm i right ??

Example:   if i put thoses configs in a tl866a programmer the same way than mplab (picture included),  the project doesn't work at all, all the parts are ok, the board too. It should enumerate as an hid interface

The project maker did sent me thoses infos

plldiv = 3
fosc = hspll_hs
cpudiv = osc1_pll2
usbdiv=2
pwrt=off
ieso=off
bor=on_active
vregen=on
wdt=off
mclre=off
pbaden=off
stvren=on
lvp=off
xinst=off
debug=off
borv=21  (for 2 volts  or 2.1 volts)

the page i have found to help me was : https://gputils.sourceforge.io/html-help/PIC18F2550-conf.html

I have conflicts understanding  theses bits

When the tl866 open the hex file it give the last picture instead

What do i miss ?

thks

[slugrustle]

You missed the terrible UI design indicator "Note: Checked = 0". Insane.

The datasheet is your friend.

Page 287, PDF Page 289:
0x300000 should be 0x22 = b'00100010' for settings
USBDIV = 1, USB clock = 96MHz PLL divided by 2
CPUDIV1:CPUDIV0 = 00, System clock = 96MHz PLL divided by 2 (WARNING: educated guess based on fosc=hspll_hs and cpudiv=osc1_pll2)
PLLDIV2:PLLDIV0 = 010, PLL prescaler divides by 3

Page 288, PDF Page 290:
0x300001 should be 0x4F = b'01001111'
IESO = 0, oscillator switchover disabled
FCMEM = 1, failsafe clock monitor enabled (WARNING: project maker did not say which).
FOSC3:FOSC0 = 1111, HS oscillator, PLL enabled

Page 289, PDF Page 291:
0x300002 should be 0x3B = b'00111011'
VREGEN = 1, USB voltage regulator enabled
BORV1:BORV0 = 11, 2.05V Typical (See PDF page 365)
BOREN1:BOREN0 = 01, Brown-Out Reset enabled and controlled by software (WARNING: guess based on "on_active")
~PWRTEN = 1, Power up reset timer disabled (Why? I've never done this)

Page 290, PDF page 292:
0x300003 should be 0x1E = b'00011110'
WDTPS3:WDTPS0 = 1111, (WARNING: using default since no guidance)
WDTEN = 0, Watchdog timer disabled, controlled by SWDTEN

Page 291, PDF page 293:
0x300005 (Where is 0x300004? Oh well...) should be 0x01 = b'00000001'
MCLRE = 0, RE3 is normal input, ~MCLR functionality disabled
LPT1OSC = 0, Timer1 configured for higher power operation (WARNING: guessing, no guidance)
PBADEN = 0, PORTB pins 4:0 are digital I/O on reset
CCP2MX = 1, CCP2 I/O multiplexed with RC1 (WARNING: default, no guidance)

Man there are a lot of configuration words.

Page 292, PDF page 294:
0x300006 should be 0x81 =  b'10000001'
~DEBUG = 1, background debugger disabled, RB6 and RB7 normal I/O
XINST = 0, Extended instruction set and Indexed Addressing disabled
ICPRT = 0, Dedicated ICSP port disabled (REQUIRED for PIC18F2550)
LVP = 0, Low voltage programming disabled
STVREN = 1, Reset on stack overflow/underflow (a wise choice)

Page 293, PDF page 295 through Page 295, PDF page 297:
Disabling all code/flash/etc.  read/write protection.
(Where is 0x300007? Oh well...)
0x300008 should be 0x0F = b'00001111'
0x300009 should be 0xC0 = b'11000000'
0x30000A should be 0x0F = b'00001111'
0x30000B should be 0xE0 = b'11100000'


This might not all be exactly as the author intended, but it will get you closer. Look over the datasheet yourself and email him with any remaining questions.

[coromonadalix]

yeah   but i was unsure ....   a "0" for me is off

the 300000 adress is bugging me with all the plldiv, cpudiv, usb div

there was a watchdog prescaller between 1:1 and 1: 32768  i could not figure ...

i did mail the author,  but no answers up to now ...

[Ian.M]

The firmware from openprog.altervista.org contains CONFIG bit setings 'prebaked' into the prebuilt HEX file, and originally defined by #pragma config directives in main.c.   Your programmer *should* accept the CONFIG settings from the HEX file as that's required by the Microchip programmer specification.  However the MiniPro software has had problems with CONFIG bit handling in the past.

N.B. MPLAB wont show the correct CONFIG bit settings until you sucessfully build the project.

Here's what MPLAB 8 reported after I imported the pre-built firmware:

 Address  Value   Field                       Setting                                   
 300000     22    PLLDIV    Divide by 3 (12 MHz oscillator input)                                           
                  CPUDIV    [Primary Oscillator Src: /1][96 MHz PLL Src: /2]                                
                  USBDIV    USB clock source comes from the 96 MHz PLL divided by 2                         
 300001     0E    FOSC      HS oscillator, PLL enabled (HSPLL)                                              
                  FCMEN     Fail-Safe Clock Monitor disabled                                                
                  IESO      Oscillator Switchover mode disabled                                             
 300002     3D    PWRT      PWRT disabled                                                                   
                  BOR       Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
                  BORV      Minimum setting                                                                 
                  VREGEN    USB voltage regulator enabled                                                   
 300003     1E    WDT       WDT disabled (control is placed on the SWDTEN bit)                              
                  WDTPS     1:32768                                                                         
 300005     00    CCP2MX    CCP2 input/output is multiplexed with RB3                                       
                  PBADEN    PORTB<4:0> pins are configured as digital I/O on Reset                          
                  LPT1OSC   Timer1 configured for higher power operation                                    
                  MCLRE     RE3 input pin enabled; MCLR pin disabled                                        
 300006     81    STVREN    Stack full/underflow will cause Reset                                           
                  LVP       Single-Supply ICSP disabled                                                     
                  XINST     Instruction set extension and Indexed Addressing mode disabled (Legacy mode)    
 300008     0F    CP0       Block 0 (000800-001FFFh) is not code-protected                                  
                  CP1       Block 1 (002000-003FFFh) is not code-protected                                  
                  CP2       Block 2 (004000-005FFFh) is not code-protected                                  
                  CP3       Block 3 (006000-007FFFh) is not code-protected                                  
 300009     C0    CPB       Boot block (000000-0007FFh) is not code-protected                               
                  CPD       Data EEPROM is not code-protected                                               
 30000A     0F    WRT0      Block 0 (000800-001FFFh) is not write-protected                                 
                  WRT1      Block 1 (002000-003FFFh) is not write-protected                                 
                  WRT2      Block 2 (004000-005FFFh) is not write-protected                                 
                  WRT3      Block 3 (006000-007FFFh) is not write-protected                                 
 30000B     E0    WRTC      Configuration registers (300000-3000FFh) are not write-protected                
                  WRTB      Boot block (000000-0007FFh) is not write-protected                              
                  WRTD      Data EEPROM is not write-protected                                              
 30000C     0F    EBTR0     Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks
                  EBTR1     Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks
                  EBTR2     Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks
                  EBTR3     Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks
 30000D     40    EBTRB     Boot block (000000-0007FFh) is not protected from table reads executed in other blocks

which is consistant with the settings in main.c:

Code: [Select]

// Define configuration registers (fuses)
// CONFIG1L
#pragma config PLLDIV = 3       // PLL Prescaler Selection bits (Divide by 3 (12 MHz oscillator input))
#pragma config CPUDIV = OSC1_PLL2// System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
#pragma config USBDIV = 2       // USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes from the 96 MHz PLL divided by 2)
// CONFIG1H
#pragma config FOSC = HSPLL_HS  // Oscillator Selection bits (HS oscillator, PLL enabled (HSPLL))
#pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
// CONFIG2L
#pragma config PWRT = OFF       // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOR = ON_ACTIVE  // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled))
//#pragma config BORV = 3         // Brown-out Reset Voltage bits (Minimum setting)
#pragma config VREGEN = ON      // USB Voltage Regulator Enable bit (USB voltage regulator enabled)
// CONFIG2H
#pragma config WDT = OFF        // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
#pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)
// CONFIG3H
//#pragma config CCP2MX = ON      // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = OFF     // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
#pragma config LPT1OSC = OFF    // Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
#pragma config MCLRE = OFF      // MCLR Pin Enable bit (RE3 input pin enabled; MCLR pin disabled)
// CONFIG4L
#pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = OFF        // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
#pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
#pragma config   DEBUG=OFF
// CONFIG5L (default)
#pragma config CP0 = OFF        // Code Protection bit (Block 0 (000800-001FFFh) is not code-protected)
#pragma config CP1 = OFF        // Code Protection bit (Block 1 (002000-003FFFh) is not code-protected)
#pragma config CP2 = OFF        // Code Protection bit (Block 2 (004000-005FFFh) is not code-protected)
#pragma config CP3 = OFF        // Code Protection bit (Block 3 (006000-007FFFh) is not code-protected)
// CONFIG5H (default)
#pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)
#pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM is not code-protected)
// CONFIG6L (default)
#pragma config WRT0 = OFF       // Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)
#pragma config WRT1 = OFF       // Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)
#pragma config WRT2 = OFF       // Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)
#pragma config WRT3 = OFF       // Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)
// CONFIG6H (default)
#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)
#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)
#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM is not write-protected)
// CONFIG7L (default)
#pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF      // Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF      // Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)
// CONFIG7H (default)
#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)

#if !defined(__18F2450)
#pragma config CCP2MX=OFF, BORV=3
#else
#pragma config BORV=21
#endif

As you can see, the contents of the 'Value' column do not match what MPLAB showed you when you simply opened main.c, probably because you didn't build the project (which would require Microchip C18).

[coromonadalix]

I did not tough of compiling it again in mplab since the hex file was available ... i dont have pickit or idc hardware ...  i have an elnec beeprog+ and a chipmaster 6000 at my job, just borrowed an tl866a from a friend, i almost totally crashed it in my win10 x64 pc with the firmware update pushed by the 6.60 version (in tl866 eevblog thread)

The Elnec is stubborn, wont accept to program it right away.

the TL866 config bit section was nearly identical to microchip specifications and naming.


Will try again tomorrow

thks

Does someone know an dallas ds24b33 cheap programmer with an gui  , i've sent an email request to add it into the tl866 minipro software.

[coromonadalix]

success     thks Ian.M  and slugrustle 

Reprogrammed it again with :  22 4F 3B 1E 00 01 81 00 0F C0 0F E0 0F 40   

Seems to be declared has vid pid 0x1209&0x5432  has the author said, had to put them in the openprog software an BAM it works, hardware tests seems fine too.

Had to boost the vusb capacitor (pic18f  pin 14)  to 10 uf,  seems to have helped   checked other kind of pic based programmers they had at least 1uf up to 10 uf for the vusb pin.

[slugrustle]

Glad it's working for you. I see you used my values, but I was guessing about several settings. Ian.M's method of opening and building the source is more accurate. He got

22 0E 3D 1E 00 00 81 00 0F C0 0F E0 0F 40

for 0x300000 through 0x30000D with 0x300004 and 0x300007 set to 00.

[Ian.M]

Actually, I didn't build it.  I used MPLAB 8, which (once the correct PIC is selected), can import a HEX file (which I got from the openprog.altervista.org site) then display all the memory areas, including decoded CONFIG bits.   MPLAB X is far far less convenient for CONFIG bit viewing/editing as it only updates when you build successfully. 

If you need to work with a HEX file from any PIC that's newer than the final MPLAB 8.92 release, five years ago, you need to use Microchip IPE (bundled with MPLAB X).  Even if you don't have a compatible programmer, it can still load a HEX file and view the CONFIG bits.  However you are S.O.L. if you need to edit them, even though it can edit other memory areas.

[coromonadalix]

Burned a second pic with the Mplab values of Ian.M 

It adds  3 more Hid_Device declarations in the device manager ... seems to work well too,  the software see's the programmer,  tests run fine too,  i've learned a few things for the config bits ...

thks @ll

I have Mplab 8.89, will try to have a more recent version without going the the mplab X