PIC 18F25K80 ceramic resonator issues

[MadScientist]

I wonder if anyone has similar experiences

We have a design using a Ztt 16mhz ( with 30pf caps ) ceramic resonator on a PIC18F25K80

Recently we’ve noticed we are getting occasional ( very occasional ) flash corruption

The BOR is set to the max ie 3V

However examining the clock suggests that the resonator is stopping very close , at or slightly above the BOR threshold , which means the clock is going out of spec in some cases before the BOR gets triggered and therefore we figure in this edge case the processor is getting corrupted and occasionally activating the flash write code

Anyone any reasons why the clock fails so , we’ve have tried both Hs1 and hs2 modes with little effect

Dave

[picandmix]

Hi,

Why don't you use the internal 16Mhz internal oscillator to prove the fault ?

[Ian.M]

I'm fairly sure that the PIC18FxxK80 series shuts off the crystal oscillator in reset the same as it does in sleep mode.  You could confirm this by applying a /MCLR reset while monitoring OSC2.

Use a pin configured as an output and set  low immediately after powerup  (do it in powerup.as if using XC8) + an external pullup resistor to monitor whether or not the device is in reset.  It will go tristate, and therefore high due to the pullup as soon as the device enters reset and go back low within a few instructions of startup if you initialise it in assembler before any C code  runs.

[MadScientist]

We can clearly see the clock is stopping as Vdd is lowered

I don’t believe the oscillator is stoped in reset. However the point is the current clock fails before the BOR reset triggers

[PCB.Wiz]

We can clearly see the clock is stopping as Vdd is lowered

I don’t believe the oscillator is stoped in reset. However the point is the current clock fails before the BOR reset triggers

3V seems rather high for any CMOS Oscillator circuit to stop, especially if started already ?
Are you sure the BOD is not the thing driving the stop.

One check would be to look for bias levels, - a disabled Osc would be Vcc/GND/floating, whilst one that failed to oscillate would be still in amplifier mode ie ~ 50% Vcc (or some linear bias point),

[KL27x]

I case you haven't already, you should probably post this on the Microchip forum. And you should check the errata for that device. And if that fails, open a ticket with Microchip customer support.

There are some other things that could be causing this, though, so make your list and check it twice. It's probably essential (or at least easiest and most efficient) to make a simpler test code just to verify that the cause-effect is what you think it is, rather than due to a bug in the code.

Some devices, for instance, you have to wait a discrete amount of time after startup/powergood before you initiate a write.
And you have to make sure your write is not interrupted (i.e. disable interrupts before any write, and reenable after it is finished).
This is maybe noob stuff, which you already know. But these are reasons to write a simple test code to isolate the problem.

So you might get a lot of other questions if you ask around. But there's a much better chance of someone else having had the same problem as you, if you post at Microchip.

[IDEngineer]

We have a design using a Ztt 16mhz ( with 30pf caps ) ceramic resonator on a PIC18F25K80... examining the clock suggests that the resonator is stopping very close , at or slightly above the BOR threshold , which means the clock is going out of spec in some cases before the BOR gets triggered

30pF seems high for that application. The device's spec sheet (DS30009977G, page 55) gives some example values and the very highest they even mention is 27pF, and that's all the way down at 4MHz. Page 55 also lists five separate Microchip application notes related to reliable oscillator operation.

They are rather explicit:

"Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application."

Note that Vdd is specifically mentioned as something to be evaluated against capacitor value. I suggest you do what they say, and characterize your circuit's performance over the expected Vdd range using your chosen ceramic oscillator while dialing in the cap values. Even if you're running from a voltage regulator, the oscillator may be unstable during power up and power down and if that happens near the BOR threshold you could get some weird effects. My gut tells me you should start by halving those caps, to around 15pF, for a 16MHz oscillator.

Hope this helps... report back!

[Ian.M]

The 'K80 can monitor its external crystal or oscillator, and if it fails, switch to internal oscillator and raise an interrupt. See datasheet section 28.5 Fail-Safe Clock Monitor, and PIR2:OSCFIF.  If you use a high priority ISR to handle OSCFIF, you could make it pulse an I/O within a very few instruction cycles of oscillator failure.  As you suspect failure occurs just above the BOR threshold, use an external flipflop to record if the pin pulses before it goes tristate during the BOR reset.

You could also try reducing the BORV threshold.  If the resonator then continues to work at a lower voltage than it did previously, that would prove the oscillator isn't failing due to undervoltage.

[MadScientist]

Thanks guys

I have created some simple test routines , which disable the BOR so that I can simply examine the clock as Vdd is lowered. It does seem that at 16Mhz , the K series pic clock is failing near 3V , which Is conincidently at the high value BORV threshold ( however with to,stance that can be as low as 2.86V )

The system is running at nominal Vdd of 5V and the frequency /voltage graph for the HD oscillator does suggest the clock should run to around 2.5V or there sbouts , one would expect the clock to certainly operate to below the highest BORV setting ( less min tolerance ) otherwise the BOR wouldn’t be any use.

I think the issue is the resonator , but resonators with alternative caps aren’t easily available so I’ve switched to a crystal design ( this board design originally cane from a non K series pic18)

We’ll see how the new clock qualification process goes in the next few days

[IDEngineer]

I think the issue is the resonator , but resonators with alternative caps aren’t easily available so I’ve switched to a crystal design

You're saying the caps are integrated into the resonator? That's unfortunate, really limits your flexibility.

I'm glad you're working with a crystal now. We use a lot of that exact part, probably over 10K pieces annually, but we use it with a quality SMT crystal and SMT caps. I think if you stick with that approach you'll be very happy.

Report back so we can all learn from what you discover!

[PCB.Wiz]

I have created some simple test routines , which disable the BOR so that I can simply examine the clock as Vdd is lowered. It does seem that at 16Mhz , the K series pic clock is failing near 3V , ...8872788

Did you check the Bias voltages at that fail point, as suggested above ? (Shows if Osc disabled, or simply stopped oscillating)
Mouser & Digikey show stocks of 16MHz resonators, with 5pF and 15pF caps, as well as ones with no caps, you could use for testing.

[KL27x]

This rings a bell. Probably a red herring, but maybe this helps.

I had issues with SMD resonators before. A few new gray hairs and four thousand dollars later, I figured out that they were failing due to overtemp during the assembly.

I checked the datasheet, and the max temperature was ridiculously low. When hand soldered with care, they worked fine. Dwell time too long, and they could get flakey. Oven reflow was just a disaster. So my initial prototype worked perfectly, of course.

I also changed to a crystal. The only reason I tried the resonators to begin with was because of the low price. They were awesomely small, though. With the integrated caps, they were truly tiny.