Typically, ADC inputs are capacitive with a small parallel resistance component (Rp ~ some megs) and a modest series resistance component (Rs ~10k).
To get rated analog bandwidth, you must have Zsrc << Rs, so that the capacitance charges at a speed limited by Rs.
To get rated gain, you also must have Zsrc < Rp / 2^ENOB, so that the voltage divider thus formed does not affect the measurement.
For Zsrc larger than these margins, gain and bandwidth will suffer. Gain can be calibrated out, and if you aren't using full bandwidth, then you'll still get the right result (given the gain error) but slower (over more than just one sample).
There may be nonlinear effects as well, like diode leakage to the pin, analog switch resistance dependence on bias, etc., which are similarly quashed when a low Zsrc is used.
Tim