PIC24 open drain I/O configuration for level down-shifting?

[smoothVTer]

We know that PICs and many MCU's offer some configurable I/O's to be set to push-pull or open drain.  In particular in PIC24 datasheets there is a mention of using the open-drain I/O setting for shifting levels up to a higher voltage.     

What about using open-drain outputs for interfacing to a lower voltage?   What are the gotcha's and traps for young players to watch out for? 

In my example target application I have to use the PIC24's  UART  to  output 1.8V  CMOS levels for interface to another device on the PCB.    Data rate is  1e6 baud.     I am able to successfully configure the PIC for open-drain IO and I use pull ups to the local 1.8V rail ( I am well decoupled ), and the system seems to work with the lower voltage.   HOWEVER:   Although the signal fall time is sharp at <15ns, the rise time to logic high 1.8V is terrible ... 175ns with 880 ohm pullups.   Originally I tried 4.7k pullups ( coming from an I2C frame of mind ) but that distorted the signal beyond the point of recognition.

Back of the envelope calculations for this rise time indicate something like a ~68pF capacitance on the open-drain pin;  this include probe tip capacitance.   Still I cannot account for the disparity between rise and fall times of my signal.   

Anyone have any experience with the rise time of open-drain IO's and could suggest possible remedies?

[JPortici]

Still I cannot account for the disparity between rise and fall times of my signal

i think it's to be expected
open drain: as in I2C you are merely putting a logic 0 or 1 on a NFET. this means that there is a device actively sinking current, but not one sourcing current, so the low to high transition (charging time) will depend on pullup and capacitance
if you need a push-pull output to keep fast transition times there are level shifters ICs

from my go-to dspic datasheet, electrical characteristic

Parameter DO56
CIO Max for All I/O Pins and OSC2 (when in EC mode): 50 pF which is consistent with your measurement

[David Hess]

Open drain outputs work fine for level shifting to a lower voltage.  Your rise time is consistent with the time constant of 68pF and 880 Ohms; it is common for open drain outputs to have slow rise times unless special measures are taken which explains why dedicated level shifters are used when high speed at low power is required.

68pF seems high though if you are using a x10 oscilloscope probe.  I would make the rise time measurement and then add enough shunt capacitance to double it.  Then the shunt capacitance will be equal to the circuit and probe tip capacitance and you will have an independent measurement of capacitance.

Update:

The high output capacitance from the datasheet identified by JPortici explains everything.

So what is it you want to accomplish?  Replacing the pull-up resistor with a current source will significantly lower the rise time if that is truly necessary.