PIC32 external osc not working

[mapexmbirch]

Hi

I have a PIC32MZ1024EF064 with a 8MHz external resonator.

http://onecall.farnell.com/murata/cstce8m00g52a-r0/resonator-ceramic-8mhz-smd/dp/2443267?ost=CSTCE8M00G52A-R0&selectedCategoryId=&categoryNameResp=All&searchView=table&iscrfnonsku=false

I have used this resonator before on a PIC18 and PIC24, both worked fine.

I can get my code to work fine with the internal FRC (8MHz), but when I switch it to the external osc, it doesn't start and it uses the other internal osc.

My setup code:

Code: [Select]

#pragma config FMIIEN = ON             // Ethernet RMII/MII Enable (MII Enabled)
#pragma config FETHIO = ON              // Ethernet I/O Pin Select (Default Ethernet I/O)
#pragma config PGL1WAY = ON            // Permission Group Lock One Way Configuration (Allow only one reconfiguration)
#pragma config PMDL1WAY = ON            // Peripheral Module Disable Configuration (Allow only one reconfiguration)
#pragma config IOL1WAY = ON             // Peripheral Pin Select Configuration (Allow only one reconfiguration)
#pragma config FUSBIDIO = OFF           // USB USBID Selection (Controlled by the USB Module)

// DEVCFG2
#pragma config FPLLIDIV = DIV_1         // System PLL Input Divider (1x Divider)
#pragma config FPLLRNG = RANGE_5_10_MHZ // System PLL Input Range (8-16 MHz Input)
#pragma config FPLLICLK = PLL_POSC     // System PLL Input Clock Selection (POSC is input to the System PLL)
#pragma config FPLLMULT = MUL_45         // System FRC Multiplier (FRC Multiply by 45)
#pragma config FPLLODIV = DIV_2         // System PLL Output Clock Divider (2x Divider)
#pragma config UPLLFSEL = FREQ_12MHZ    // USB PLL Input Frequency Selection (USB PLL input is 12 MHz)

// DEVCFG1
#pragma config FNOSC = SPLL          // Oscillator Selection Bits (Primary Osc (HS,EC))
#pragma config DMTINTV = WIN_127_128    // DMT Count Window Interval (Window/Interval value is 127/128 counter value)
#pragma config FSOSCEN = OFF            // Secondary Oscillator Enable (Disable SOSC)
#pragma config IESO = OFF                // Internal/External Switch Over (Disabled)
#pragma config POSCMOD = HS             // Primary Oscillator Configuration (HS osc mode)
#pragma config OSCIOFNC = OFF           // CLKO Output Signal Active on the OSCO Pin (Disabled)
#pragma config FCKSM = CSDCMD           // Clock Switching and Monitor Selection (Clock Switch Enabled, FSCM Enabled)
#pragma config WDTPS = PS1048576        // Watchdog Timer Postscaler (1:1048576)
#pragma config WDTSPGM = STOP           // Watchdog Timer Stop During Flash Programming (WDT stops during Flash programming)
#pragma config WINDIS = NORMAL          // Watchdog Timer Window Mode (Watchdog Timer is in non-Window mode)
#pragma config FWDTEN = OFF             // Watchdog Timer Enable (WDT Disabled)
#pragma config FWDTWINSZ = WINSZ_25     // Watchdog Timer Window Size (Window size is 25%)
#pragma config DMTCNT = DMT31           // Deadman Timer Count Selection (2^31 (2147483648))
#pragma config FDMTEN = OFF             // Deadman Timer Enable (Deadman Timer is disabled)

// DEVCFG0
#pragma config DEBUG = OFF              // Background Debugger Enable (Debugger is disabled)
#pragma config JTAGEN = OFF             // JTAG Enable (JTAG Disabled)
#pragma config ICESEL = ICS_PGx1        // ICE/ICD Comm Channel Select (Communicate on PGEC1/PGED1)
#pragma config TRCEN = ON               // Trace Enable (Trace features in the CPU are enabled)
#pragma config BOOTISA = MIPS32         // Boot ISA Selection (Boot code and Exception code is MIPS32)
#pragma config FECCCON = OFF_UNLOCKED   // Dynamic Flash ECC Configuration (ECC and Dynamic ECC are disabled (ECCCON bits are writable))
#pragma config FSLEEP = OFF             // Flash Sleep Mode (Flash is powered down when the device is in Sleep mode)
#pragma config DBGPER = PG_ALL          // Debug Mode CPU Access Permission (Allow CPU access to all permission regions)
#pragma config SMCLR = MCLR_NORM        // Soft Master Clear Enable bit (MCLR pin generates a normal system Reset)
#pragma config SOSCGAIN = GAIN_2X       // Secondary Oscillator Gain Control bits (2x gain setting)
#pragma config SOSCBOOST = OFF          // Secondary Oscillator Boost Kick Start Enable bit (Normal start of the oscillator)
#pragma config POSCGAIN = GAIN_2X       // Primary Oscillator Gain Control bits (2x gain setting)
#pragma config POSCBOOST = ON           // Primary Oscillator Boost Kick Start Enable bit (Boost the kick start of the oscillator)
#pragma config EJTAGBEN = NORMAL        // EJTAG Boot (Normal EJTAG functionality)

I have no idea what you should look for when selecting an resonator.

When I probe the pins there is about 0.5V of DC on one pin and 0V on the other.   A picture of how I connected it to the PIC is attached.

Any help would be greatly appreciated!

[Lunasix]

There is an errata for PIC32MZ and external resonator ! Verify your silicon revision.
I prefer an external oscillator, work always.

[rcbuck]

I think you are referring to the PIC32MZ1024EFE064.

Errata for the part says this:
Revision  A1  Silicon: A  crystal  oscillator  cannot be  used  as  an  input  to  the  Primary  Oscillator (POSC) pins OSC1 and OSC2.

Revision A1 Silicon Work around
Use   an   external   clock   or   the   Internal   FRC

They are showing the same problem for Revision A2. Rev A3 doesn't appear to have the problem but does require a very specific oscillator circuit. See the errata sheet here:

http://ww1.microchip.com/downloads/en/DeviceDoc/80000663D.pdf

[mapexmbirch]

Thanks for the replies guys.

I have replaced the resonator and applied a bit more solder to the pins,and still nothing.

I think I have revision E3.  That's what it says on the top, not sure if that is the revision number or not.  See attached.

I think I might use this osc which is used on the development board:
http://www.microchip.com/_ImagedCopy/microchiptechnologyinc_30262490421.jpg
http://www.digikey.com/product-detail/en/microchip-technology/DSC1001BC1-024.0000/DSC1001BC1-024.0000-ND/6192838

[JPortici]

the silicon revision is the one listed when the programmer / debugger is connected to the pic

[Abstr7ct]

You should load the resonator by 10pF capacitance. Typical circuit connection is shown below for your part.

[mapexmbirch]

Ah it's A1.

It says on the errata, the work around is to use an external clock.  Which pin do I apply this to?  Is it OSCI/CLKI?

[JPortici]

yes

question: what could one use ad an on board external clock source?

[mapexmbirch]

Something like this:
http://www.digikey.com/product-detail/en/microchip-technology/DSC1001BC1-024.0000/DSC1001BC1-024.0000-ND/6192838
or this
http://onecall.farnell.com/abracon/asemb-24-000mhz-ly-t/mems-osc-24mhz-3-2-x-2-5mm-lvcmos/dp/2467910

[Niklas]

This issue is fixed on the A2 and A3 silicon revisions. One interesting feature with this bug is that it will brick the JTAG interface halfway through a firmware download. If that happens, then ICSP can be used to erase the device and bring it back to life.