This looks super sketchy. Strong redirect to on-line tool, command line one seems to be checking in with on-line and there does not seem to be a source code available despite the claims of being GPL3 licensed.
I don't want to start a holy war, but what you are looking for is SystemVerilog. It is supported (in parts) by most modern tools from actual FPGA vendors and improves quite a bit on Verilog, but still maintains simple and readable syntax.