plz help me on this code

[navidrct]

hi
what lib should i include to use LPC_ADC instruction?
what is 1UL in this code?what does it mean?
im new in this.if u can comment this code more than this i apericiate it
thanks

Code: [Select]

LPC_ADC->ADCR = 0; // Power AD down
  LPC_SC->PCONP |= (1 << 12); // Enable power to AD block
LPC_SC->PCLKSEL0 &= ~(1<<24); // clock 25 MHz
LPC_SC->PCLKSEL0 &= ~(1<<25);
LPC_ADC->ADCR = 7 << 8; // conversion clock = 100 Mhz / 8 [7+1] = 12.5 MHz
LPC_ADC->ADCR |= (1<<21); // PDN = set AD operational
LPC_ADC->ADCR |= (1<<0); // SEL = select AD0.0 to start

int Good = 1;
int Bad = 0;
while(1)
{
LPC_ADC->ADCR |= (1<<24); // START = start conversion now
while (!(LPC_ADC->ADGDR & ( 1UL << 31)))
;  /* Wait for Conversion end       */
int value = (LPC_ADC->ADDR0 >> 4) & 0xFFF;
if((value < 0x580) || (value > 0x5FF))
Bad++;
else
Good++;
double pct = (double)Bad * 100 / (double)Good;
Debug("AN0 = %X good %5d bad %5d %.02f%%", value, Good , Bad, pct);
os_dly_wait(25);
}


[f1rmb]

UL is for unsigned long type.

Cheers.

[navidrct]

UL is for unsigned long type.

Cheers.

( 1UL << 31)
then this line of code say 31 time shift to left an unsigned long?
y use this ? can u explain to me?

[hamster_nz]

UL is for unsigned long type.

Cheers.

( 1UL << 31)
then this line of code say 31 time shift to left an unsigned long?
y use this ? can u explain to me?

The unsigned long is set explicitly as in some environments 'int's are 16-bit.

If you shift a 16-bit int to the left 32 times you end up with zero - and a hard to track down bug, as everything looks correct!

[slateraptor]

UL is for unsigned long type.

Cheers.

( 1UL << 31)
then this line of code say 31 time shift to left an unsigned long?
y use this ? can u explain to me?

It looks like you've extracted that from the following code:

      while (!(LPC_ADC->ADGDR & ( 1UL << 31)))
            ;  /* Wait for Conversion end       */

This is typical C-style bitwise manipulation.


SUMMARY DESCRIPTION:
In this device's architecture, LPC_ADC->ADGDR is at least a 32-bit status/control register. When A/D conversion is complete, the device will set bit 31 (0-indexed; MSB). The while loop prevents the program from moving forward until this bit is set.


STEP-BY-STEP SYNTHESIS AND INTERPRETATION:

1.) 1UL

In binary, this looks like:
MSB                                 LSB
31                                    0
0000 0000 0000 0000 0000 0000 0000 0001  // 1UL

This is interpreted as decimal 1 represented as unsigned long type. Long type, in this case, is clearly mapped to 32-bit representation. A 2's complement (aka signed) integer representation uses the MSB to differentiate positive and negative numbers...the next step will make clear why UL is used.


2.) 1UL << 31

In binary, this looks like:
MSB                                 LSB
31                                    0
1000 0000 0000 0000 0000 0000 0000 0000  // 1UL << 31

This is interpreted as 1UL left-shifted 31 times. Arithmetically, left-shifting an unsigned integer is the decimal equivalent of multiply-by-2 for each shift, so the statement is the same as 1 x 2³¹ = 2,147,483,648, which is precisely 1 unit more than the highest positive integer that can be represented by 32-bit 2's complement, consequently resulting in an overflow condition if signed integer representation (the default option) were used.

This is done for code readability and clarity of intent. The device doesn't really perform the left-shift operation on a predefined constant...that's simply waste. The compiler will inevitably optimize this down to something efficient but a lot less meaningful to a human reader (think "magic numbers").


3.) LPC_ADC->ADGDR & (1UL << 31)

In binary, this looks like:
MSB                                 LSB
31                                    0
Txxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx  // LPC_ADC->ADGDR
1000 0000 0000 0000 0000 0000 0000 0000  // 1UL << 31
---------------------------------------
T000 0000 0000 0000 0000 0000 0000 0000  // LPC_ADC->ADGDR & (1UL << 31)


For the ADGDR register, T represents the target status bit and x represents bits whose values we don't care about (they can be any state). & is the bitwise AND operator, which is used to mask off the bits we don't care about, extracting just the target bit in question...(0 & wuteva) always returns 0. On the other hand, (1 & wuteva) returns the value of wuteva.

This means there are only 2 possible states for the expression LPC_ADC->ADGDR & (1UL << 31):

0000 0000 0000 0000 0000 0000 0000 0000 = 0
1000 0000 0000 0000 0000 0000 0000 0000 = 2,147,483,648 (not 0)


4.) !(LPC_ADC->ADGDR & (1UL << 31))

! is the logical NOT operator, which is boolean...in other words, if 0 return FALSE, otherwise return TRUE. Putting this together with...


5.) while(!(LPC_ADC->ADGDR & (1UL << 31)));

...the while loop is TRUE (or not FALSE) and loops indefinitely doing nothing (; immediate termination) until the target bit T is set.

When the A/D conversion is complete, the device will set the T bit, which will subsequently break out of the loop and proceed to handle the converted data.

[navidrct]

UL is for unsigned long type.

Cheers.

( 1UL << 31)
then this line of code say 31 time shift to left an unsigned long?
y use this ? can u explain to me?

It looks like you've extracted that from the following code:

      while (!(LPC_ADC->ADGDR & ( 1UL << 31)))
            ;  /* Wait for Conversion end       */

This is typical C-style bitwise manipulation.


SUMMARY DESCRIPTION:
In this device's architecture, LPC_ADC->ADGDR is at least a 32-bit status/control register. When A/D conversion is complete, the device will set bit 31 (0-indexed; MSB). The while loop prevents the program from moving forward until this bit is set.


STEP-BY-STEP SYNTHESIS AND INTERPRETATION:

1.) 1UL

In binary, this looks like:
MSB                                 LSB
31                                    0
0000 0000 0000 0000 0000 0000 0000 0001  // 1UL

This is interpreted as decimal 1 represented as unsigned long type. Long type, in this case, is clearly mapped to 32-bit representation. A 2's complement (aka signed) integer representation uses the MSB to differentiate positive and negative numbers...the next step will make clear why UL is used.


2.) 1UL << 31

In binary, this looks like:
MSB                                 LSB
31                                    0
1000 0000 0000 0000 0000 0000 0000 0000  // 1UL << 31

This is interpreted as 1UL left-shifted 31 times. Arithmetically, left-shifting an unsigned integer is the decimal equivalent of multiply-by-2 for each shift, so the statement is the same as 1 x 2³¹ = 2,147,483,648, which is precisely 1 unit more than the highest positive integer that can be represented by 32-bit 2's complement, consequently resulting in an overflow condition if signed integer representation (the default option) were used.

This is done for code readability and clarity of intent. The device doesn't really perform the left-shift operation on a predefined constant...that's simply waste. The compiler will inevitably optimize this down to something efficient but a lot less meaningful to a human reader (think "magic numbers").


3.) LPC_ADC->ADGDR & (1UL << 31)

In binary, this looks like:
MSB                                 LSB
31                                    0
Txxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx  // LPC_ADC->ADGDR
1000 0000 0000 0000 0000 0000 0000 0000  // 1UL << 31
---------------------------------------
T000 0000 0000 0000 0000 0000 0000 0000  // LPC_ADC->ADGDR & (1UL << 31)


For the ADGDR register, T represents the target status bit and x represents bits whose values we don't care about (they can be any state). & is the bitwise AND operator, which is used to mask off the bits we don't care about, extracting just the target bit in question...(0 & wuteva) always returns 0. On the other hand, (1 & wuteva) returns the value of wuteva.

This means there are only 2 possible states for the expression LPC_ADC->ADGDR & (1UL << 31):

0000 0000 0000 0000 0000 0000 0000 0000 = 0
1000 0000 0000 0000 0000 0000 0000 0000 = 2,147,483,648 (not 0)


4.) !(LPC_ADC->ADGDR & (1UL << 31))

! is the logical NOT operator, which is boolean...in other words, if 0 return FALSE, otherwise return TRUE. Putting this together with...


5.) while(!(LPC_ADC->ADGDR & (1UL << 31)));

...the while loop is TRUE (or not FALSE) and loops indefinitely doing nothing (; immediate termination) until the target bit T is set.

When the A/D conversion is complete, the device will set the T bit, which will subsequently break out of the loop and proceed to handle the converted data.

thanks alot
so helpful