poblems with capturing the sine wave by ADS131e08 and display it by Chipscope!

[javad2040]

Hi guys,
I designed a Data Acquisition system with ADS131e08 ADC and spartan6 FPGA.
I config the ADC and read data from it by my vhdl code that it contains several States. In this states, the ADC first reset and then the Config registers sets correctly.

I set the ADC parameters to:
CONFIG1 = 0xD2 , CONFIG2 = 0xF0 , CONFIG3 = 0xC0
CH1SET = 0x10 , GAIN1 = 1 , MUX1 = 000 (normal input)
CHnSET = 0x90 , n = 2...8 this channel power downed

and

Fclk= 2.048 MHz
Fsclk = 18.432 MHz
Data Rates : 16 KSPS
RESOLUTION = 24bit
AVDD = +2.5v
AVSS = -2.5v
sine Wave (peek to peek = 2v) that is less than the ADC Vp-p = AVDD - AVSS.

I use sine wave with frequency 50 Hz that period of it is 20ms. I sample the sine wave 256 times with ADC that total frequency is 256 x 50Hz. I produce this frequency by counter and send it to the Xilinx ChipScope and received data is semi-sine wave and has distortion (below figure) that must be sine wave because of ADC resolution (24 bit).

I use oscilloscope to saw the sine wave, the Vp-p of it is whole 2v that is safe and less than the ADC inputs Vp-p.
ALso i use the RDATA mode and set the VDD=3.3v that SCLK is 54 ns and when i connect the ADC board to the power, it inject the noise to sine wave and change the peaks of it(the figure captured by oscilloscope has shown), but when i disconnect the ADC board, the noise removed and sine wave be corrected.

I use the ADS131e08 evaluation board schematic to design the board that pdf of schematic has uploaded.

please help me to solve the problems(remove the injected noise and receive and capture the sine wave exactly).

best regards,

[hamster_nz]

Are your inputs locked in to the IOB?

Have you put the proper timing constraints in?

As a quick test, try latching the data serial data in the FPGA on the other clock edge (e.g. falling_edge() instead of rising_edge()) and see if that helps..