Yes. DEBUG should *NEVER* be enabled for a release build. The breakpoint register(s) default to having a breakpoint at address 0 enabled after reset (which is why a NOP at address 0 is recommended when debugging) Normally this is used to let the debugger handshake with the debug executive and initialise debugging. What happens when execution jumps to the debug vector with no debug executive is a pure gamble. Interrupts will be disabled and peripherals are likely to be frozen and where it goes to next is anyone's guess.
With LVP enabled, a high level or floating RB5/PGM pin can cause intermittent operation, by causing the PIC to enter ICSP programming mode, which halts it and resets it on exit.
Generally you should enable BOR, and set it to the minimum for your part and enable PWRT. Exceptions can be made if the power source switch-on and switch off are well characterised and meet the initial minimum voltage and risetime specs, or if you are using an external reset controller. One of the known misbehaviors of the Microchip 8 bit cores when the supply voltage is out of spec is that they can 'blow through' conditional instructions and its suspected jumps etc. as well. i.e. the program counter will continue to increment and instructions will continue to be fetched at a lower voltage than the CPU can properly execute them at. This known misbehaviour normally shows up as random EEPROM (or FLASH) corruption after a brownout, caused by the EEPROM/FLASH write unlock sequence getting inadvertently executed.
As any code in memory may be executed, including any CLRWDT instructions present, this can defeat the watchdog. I certainly wouldn't trust the CPU to resume normal operation correctly when the voltage rises again without a Reset signal.