precise high res pwm

[acbern]

does anybody have a suggestion how to simply generate a 20 to 24 bit pwm. cpld/fpga, ok, but quite an effort (for me at least, have nil experience with it).
rather thinking of programming a microcontroller pwm output, but those I found have 16 bits max.
this is for generating a very precise voltage. so the accuracy of the pwm is important (should basically be defined by the osc. used).
(and no, a calibrator is not the solution, I need a part; also, the analogs arround I will take care, so really the issue is the digital part).
frequency of some ten to 100 hz would be ok (given max frequency of input)
there is a solution shown in edn, using different control signals and analog switches, but has other drawbacks.
looking realy for a microcontroller based solution.

adrian

[mikeselectricstuff]

You can increase effective resolution of a MCU PWM using dithering - e.g. change the LSbit every nth PWM cycle.
You will struggle to  get high res with plain PWM though due to the difficulty of ripple filtering to get a sensible settling time.
If you need 20-24 bits you probably should be using a proper DAC, or at least looking at the techiques that proper DACs use, which will certainly not look much like PWM. 

Some 32 bit MCUs will support 32 bit PWM by the nature of the counters they use to do it - certainly some of the NXP ARMs will.

However look at the figures - say you have 20 bits with a PWM clock of 50MHz, this will give you a 47Hz PWM cycle. What sort of filter time constant are you going to need to filter out that ripple down to the LS bit? well under 1Hz I'd expect. 

[dannyf]

how to simply generate a 20 to 24 bit pwm. ...

this is for generating a very precise voltage.

Are you trying to generate 20/24 bit pwm or are you trying to generate very precise voltage? It is perfectly fine to generate very precise voltage using <20 bit pwm.

But if you insiste on 24-bit pwm, mcus are practically out of the question for the frequency you need.

[acbern]

thanks guys so far.
few comments: the filtering is a resolved issue. I do not want to dig into this given this is a digital blog. also, i do not need fast settling.
pwm at this accuracy level is in principle the best soultion, the most accurate calibrators out there use this. the digital part is an issue, am still trying to avoid cplds. really stable dacs at this resolution do not exist. the most accurate i know of is from ad, it has other potential drift issues and is 20 bit 'only'.

[madires]

Some AVR32 got 20 bit PWM.

[AndyC_772]

In what way would a digital output from a MCU, toggling up and down somewhere around the mains frequency, actually qualify as 'more stable' than a dedicated DAC device designed for the purpose?

What characteristics are you expecting of the digital device's output in each of its two states? When it's a logic '1' it'll be equal to the local supply voltage (whatever that's doing), minus some temperature and load dependent figure, plus some interference from the inside of the chip. Logic '0' doesn't have the same PSU dependency, but it's still not exactly 0V, ever.

How are you powering this digital device of yours? If you're relying on your logic '1' output level to be constant, then if the supply voltage is meant to be 3.3V, but it drifts up to 3.300003V, that's one LSB of error at 20 bits. Where is your PSU getting its voltage reference from, and what is the drift in its control loop?

Let's suppose you can generate a PWM signal at 100 Hz, which you can do to 20 bit precision with an FPGA running at 100 MHz or thereabouts. Let's also suppose that you have an "ideal" digital buffer on the output which delivers absolutely precise, repeatable logic levels, with no noise or drift whatsoever. What then? You need a filter which drifts by less than one LSB in 10 msec in order to keep the output stable.

Full scale at 20 bits is about a million LSBs. If your filter takes >10ms to change its output by 1 LSB, then a full scale change of output will take a million x 10ms, which is nearly 3 hours.

[sync]

I was experimenting with PWM + dithering using an ATmega and a 74HC14 as driver. One of my best results I got with 10 bit PWM + 14 bit dithering (see attachment). At the low and high end there were substantial nonlinearities. I used several calibration points (100uV, 5mv, 1V and 4V) to compensate it at the low end. Also I had spikes like between 3.6 - 3.7V of the graph. At these the precision wasn't good. There was a hysteresis depend to the direction of the voltage change. The settling times were a few 10s.

In the end I gave up on this PWM idea.

[T3sl4co1l]

If you need more bits than a given counter register, you can do sigma-delta on it.  S-D isn't just a one-bit thing, the general case applies for any number of bits.  Instead of a comparator, you need an ADC.  Which will of course limit your accuracy -- you can't expect an ENOB of 20 with an ADC that hardly does 11 bits in DNL or INL.

Let's suppose you can generate a PWM signal at 100 Hz, which you can do to 20 bit precision with an FPGA running at 100 MHz or thereabouts. Let's also suppose that you have an "ideal" digital buffer on the output which delivers absolutely precise, repeatable logic levels, with no noise or drift whatsoever. What then? You need a filter which drifts by less than one LSB in 10 msec in order to keep the output stable.

Full scale at 20 bits is about a million LSBs. If your filter takes >10ms to change its output by 1 LSB, then a full scale change of output will take a million x 10ms, which is nearly 3 hours.

Fortunately, a LTI (linear time-invariant) filter does not exhibit slew rate limiting.  A single pole cutoff at 100Hz will let through almost all the ripple, but has a 20 bit settling time of around 14ms, for a full scale transition.

Of course, a 100Hz single pole lets through about 70% ripple.  You'd want to use a lower cutoff many-pole filter.  The same general idea applies though.

Note also, if your spec is settling within +/- 1 bit inclusive, a transition of <1 bit will settle almost instantaneously.

Tim

[acbern]

the atmel at32 was a good hint, thanks madires. works up to 100+ mhz pwm clock, that also gives a reasonable output frequency.
of course, one needs very dc-stable and steep filters, but its doable this way as it looks.

settling is also solvable, to those who are concerned (at least within the timeline I need, couple seconds).

and of course, the voltage being pwm'ed needs to be very stable, the output cannot be more stable than it, for obvious reasons, so one would use a voltage with <1ppm stability to do that given the 20 bit equate about 1ppm. using the digital voltage does not make any sens of course as andyc_772 points out.

[dannyf]

the voltage being pwm'ed needs to be very stable, the output cannot be more stable than it, for obvious reasons

For obvious reasons, a super stable supply voltage isn't always required: it is implementation specific.

[Jeroen3]

Find an ADC that accurate and create a closed loop pwm voltage regulator using PID.
Or am I missing some important detail why 32 bit timers wont work here?

*ST parts have 32 and 16 bit timers, NXP parts mostly have 32 bit timers only, also most other modern parts can concatenate timers.

[acbern]

thanks, but thats timers, and not pwm. or do you have somthing specfic in mind capable of doing beyond 20 bits pwm?

and an adc introduces other isses (linearity, offset and full scale drift, aging...), getting all this under control is much more expensive than the pwm solution. plus you still need a precise/high res. pwm.

[mikeselectricstuff]

thanks, but thats timers, and not pwm.

PWM is sometimes just a particular timer configuration. You can potentially use timer compare hardware to do PWM if not directly supported by timer hardware.

 

[dannyf]

but thats timers, and not pwm.

They (and OC) are the same thing.

or do you have somthing specfic in mind capable of doing beyond 20 bits pwm?

Too many to list. But if you do the math, to generate 32-bit pwm at even 1Hz means the mcu has to run so fast that you are unlikely to have this type of devices unto 2050, at the earliest.

and an adc introduces other isses (linearity, offset and full scale drift, aging...), getting all this under control is much more expensive than the pwm solution. plus you still need a precise/high res. pwm.

You may want to read AN86 from Linear.

[David Hess]

Find an ADC that accurate and create a closed loop pwm voltage regulator using PID.
Or am I missing some important detail why 32 bit timers wont work here?

*ST parts have 32 and 16 bit timers, NXP parts mostly have 32 bit timers only, also most other modern parts can concatenate timers.

This is how I have seen it done in the past although two DACs were used as the source.  20 bit linear integrated ADCs are inexpensive and easy to use.  I have considered a similar design using charge balancing instead of DACs or PWM.

[acbern]

using only 22 bits of a 32 bit counter would be sufficient. 32 bits as you state obviously takes too long. while 20 bits would be ok, 22 would be desirable for my application. the key really is to find a micro-c. that has hardware capabilities in the counter stage to generate an output resuting in a pwm. Just setting a counter and counting down will not do it. the tricky part is the hw logic arround the counter stages. I am not the microcontroller speciialist (thats why I am asking you guys), but have not found a suitable controller yet. The only fit was the AT32 above as recommended by madires.

And thanks, I know AN86 (also other interesting stuff included), but I always found this approach way too complicated and costly compared to a PWM solution (dont forget the digital stage which also requires a microcontroller). The goal here really is simple and low cost and precise. two dacs and an adc and a micro-c is much more costly than an at32, a chopper and a filter stage.

[AndyC_772]

Assuming you really do have your digital buffering, power supply and analogue filtering sorted, could you achieve what you want with two separate PWM outputs to give you 'coarse' and 'fine' adjustment?

Set up your output buffer / amplifier network such that one output has a gain of, 1:1, and the other is added with a gain of, say, 1/4096. Set the output voltage to be approximately the right value with the first PWM output, then trim it up or down very slightly by adjusting the duty cycle of the other.

Major advantage: in a perfect world, two 12 bit PWM outputs with suitably weighted outputs gives you 24 bits' worth of precision. Counter frequency can be dramatically reduced, and your filter design may actually have a chance of working.

Disadvantages: all sorts of things to do with component matching, drift and so on.

[mikeselectricstuff]

simple and low cost and precise

Pick two.
You get what you pay for.

[acbern]

yes, in principle a good idea, but as you point out, the problem is with the matching of the two (at least at 16 bit each). in addition, the stability of the whole thing will only be as good as the msb stability, which is now also analog. as I am moving the mixing into the analog world, all the usual drift and aging issues would show up. overall, even if it worked out (I have not done a error propagation calculation), I think the 20 bit pwm solution is still more simple.
what I was thinking about is using 2x 20bit pwm (the at32 has 4), one to achieve 1ppm resolution, the other to do sub-ppm (of coarse even 8 bit would be sufficient for that). if properly done, the drift impact is neglectable there. 

[AndyC_772]

Is the matching that big a deal? If both of your digital output buffers are powered from the same supply then they'll drift together, and if they both connect to the same analogue filter then that shouldn't introduce any mismatch either.

What you need are two resistors at the input to the filter, which maintain an accurate (and known) resistance ratio. Mount two high quality resistors of the same type next to each other and in good thermal contact, and I don't see why it shouldn't work.

[acbern]

so very quick sanity check:
for 16 bit, an lsb equates about 150uv at 10v. if I wanted the drift from mixing to be less than 1uv, equal 0.1ppm at 10V (per year and over 20K temp range) that would equate about 0,7% of drift related to the 150uv, or 7000ppm. aging of good resistors is maybe 25ppm each pa, 50 ppm for both. affordable resistors are 5ppm/k, thats another 200ppm combined. so seems to work with 2x 16 bit pwm.
one thing to observe is mixing ratio. relation is 1:64k, so e.g. 100 ohms versus 6.4 meg. so leakage (moisture, solder flux residues) must be observed in the design. respectively, one could limit the voltage swing of the ls pwm dac and decrease the 6.4meg resistor value accordingly, this would be the better approach.
on a side note, using normal dacs for both will not do it as the zero/full scale drift of the msb is prohibitive.

[dannyf]

Is the matching that big a deal?

It would be trivial in a feedback loop; In open loop controls, it can be significant.

[Smokey]

Check out TI DSPs.  This is just one app note.  A lot of the TMS chips have the high resolution PWM.

http://www.ti.com/lit/ug/spruge8e/spruge8e.pdf

[Andreas]

does anybody have a suggestion how to simply generate a 20 to 24 bit pwm.
looking realy for a microcontroller based solution.

You can either try a PIC24FV32KA302 (two 16 Bit timers can be concatenated to build a up to 32 bit counter or PWM)
or simply use 2 16 Bit PWMs mixed together via resistors.

Essential is that you use switches with high symmetry and low charge injection. (a HC-MOS gate is far away from that).
Up to now I have best results with MAX4053A devices.
A good starting point would be this cirquit
http://edn.com/design/other/4326640/DC-accurate-32-bit-DAC-achieves-32-bit-resolution
 
I got 16 bits linearity from start and could trim this to around 2-3 ppm by adjusting R7.
The advantage of this cirquit is very fast settling time (with proper adjustment).
The disadvantage is noise (compared to a DAC solution) from switching.

With best regards

Andreas

[Andreas]

I think the 20 bit pwm solution is still more simple.

This will only be so long until you really tried it.
A difference in rise/fall time of 10 ns at 100 Hz will be already 1 ppm non linearity.
A charge injection of 10 uC will charge up your 1uF filter capacitor by 10 uV.
Different output resistance in high and low state will do their job.
Not to speak from digital effects like "ground bouncing".
And all effects are temperature dependant.

Don't think that a digital design is more easy when its going to ppm level.

With best regards

Andreas