problems with programming Spartan XC3s100E

[lincoln]

Hello,

I have a new board that i'm having problems getting running. So far the only things populated on the board are power, decoupling caps, FPGA (XC3s100E), spi flash and jtag header. I am using the "JTAG-HS3" form diligent as a programmer.  When I fire up iMPACT, It completes the boundary scan.  But any other operations fail, Get device Id, program, get device signature,  Digilent's software also don't read the device.

For the hardware, The IO banks are 3v3, Jtag is running at 2.5, cor voltage is 1.2.

- Done signal is pulled up with 330 ohm to 2.5 v
- init b is pulled up to 3.3v with 4.7k
-hswap is pulled low with 360 ohm,
- TCK is terminated,
- TMS and TDI are pulled up to 2.5v with 10k,
- The desing originaly had a mux to switch between the jtag headder and a ftdi usb chip  but I have pulled it off and blue wired the jtag hedder to be the only option
- I have poked the pins on the FPGA with an oscope and things seem reanable but then again i don't know what i'm looking for.
- CCLK was initially not terminated, then terminated, then removed the flash chip, and then re-terminated. all permutations had no effect.
- the board has been cleaned of flux and what not, Also did see any whiskers under magnification...

Any Ideas?

[nctnico]

330 Ohm is way to low for a pull-up. Use 4.7k Ohm.

[Someone]

330 ohm is their reccomended value, and 4k7 would be too high, you might want to keep off the advice if you don't know the parts. The done pin is quite a complex function and can be configured to do all sorts of complex things that will interfere with configuration so following the configuration guide examples is usually a good idea.

The SPI flash shouldn't have any affect on addressing the FPGA over JTAG, have you tried running the clock of the JTAG interface slower? The digilent adaptors can be quite flakey compared to the current Xilinx pod. Also have you scoped the power rails while it's powering on and during JTAG access?

[lincoln]

Hello,
   Thank you for your replies. It winds up my JTAG is a mess, with the MUX in place the 10k was not a strong enough pull up and with the mux removed form the board, there was a whisker connecting it to the other jtag source creating a stub.

>The SPI flash shouldn't have any affect on addressing the FPGA over JTAG

Right but if I read the documentation right CCLK is used internally as well so if it connected to anything, proper termination is required.

>Also have you scoped the power rails while it's powering on and during JTAG access?

I did but all I see is common mode crap, and noise from my switching bench supply. The on board power is actually doing a pretty good job of filtering out the supply noise. I will check it again when I can get a linear power supply free and turn off other things in the lab.

Thank you for your help, I was out of yarn yesterday.