[SOLVED]Programming the DE0-Nano

[sci4me]

Hi guys, so I am getting my de0-nano in tomorrow, and right now, I'm trying to get all the software set up. I have seen on multiple websites that I should use Quartus II... and when I went to the site, I saw that its not free. So... 1. do I NEED to have this software? 2. are there free versions that work about as well... Because I really don't want to have to pay more money for now... I know there is a 30 day trial, but I wont just stop programming my fpga after 30 days...

[olsenn]

Altera has what they call the "Web Edition" of Quartus which is free software. It comes on CD with the DEO Nano as well as example software for you to play with.

[sci4me]

How bad are its limitations?

[olsenn]

There won't be any for you. The free version of Quartus doesn't work with the larger, more expensive FPGA chips, but the Cyclone IV in the DE0 Nano is obviously one of the ones it can program. Also with the paid software you can get some pre-written IP if you needed some commonly used piece of (soft) hardware, like audio codecs, HDMI controllers, etc. These things can be found online for free anyways in most cases (check out OpenCores). Lastly, I believe the Web Edition of the software has some limitations to use of Nios, the soft core microprocessor made for Altera FPGA's, but I'm not too sure about that one.

If Dave's video was the only introduction you've had to FPGAs, then I would STRONGLY suggest you pick up the book "Digital Design Using Digilent FPGA Boards" from the site below. Verilog is closer to C then VHDL, so you may want to go with that version.

http://www.lbebooks.com/booksandkits-HWDesignVerilog.htm#verilogDigilent

[sci4me]

I've had a bit more introduction to FPGA's than Dave's video, but I still am basically an absolute beginner as far as programming and using them goes. As far as the book goes, Ill check it out. Also, I have been thinking to use verilog over vhdl because of the examples I've seen. It does look easier to use to me.

[marshallh]

My advice: don't learn verilog or vhdl, learn _digital design_
Verilog is just how you punch it in to the computer. If you want to see what happens when software-only guys take a crack at digital design, look no further than Opencores

[JorgeCarbajal]

You should be fine with the web edition, even with it you can try some IP included, you can program the device but it has to be connected to the pc all the time if you choose to use them. You can find from memory controllers to DSP functions like FFT cores and such.
I'm pretty sure you will receive a CD ROM containing the software you need, but if you need like downloading it right away you can get the web edition for free (after signing up with altera).

[free_electron]

My advice: don't learn verilog or vhdl, learn _digital design_
Verilog is just how you punch it in to the computer. If you want to see what happens when software-only guys take a crack at digital design, look no further than Opencores

opensores...

@Ts : quartus web edition is free. the difference :
-  web edition tops out at about 25 million gates . so you won;t be able to program the devices that cost more than 1000$...
- doesn't do all families. the families it cannot do are all 1000$ +
- no incremental compilation . irellevant unless you do million gate designs as it shortens synthesis time
- cores (like nios et al) work for 1 hour , then stop. you need to powercycle the pcb to get another hour. if you don't use those cores there is no problem.

[Berni]

I have used it for some time now and it has no serious show stopper disadvantages. You also get quite a bit of IP with it for free like memory controllers and misc simple stuff. But the more advanced IP you can evaluate for 1 hour from board power up or for an infinite amount of time if you keep your board connected trough JTAG.

The full version also can use up to I think 8 CPU cores for compilation and incremental compilation to reduce your compile time as it gets really anoint to have to wait 10 minutes for your design to compile just because you had to change 1 line of code somewhere. You need a sizable design to make it compile that long but even simple hello world things take 30 seconds to 1 minute to compile on large chips. It's just a bit of an annoyance when you are used to a few second incremental compiles in your huge C programs.

[ChrisW]

My advice: don't learn verilog or vhdl, learn _digital design_
Verilog is just how you punch it in to the computer. If you want to see what happens when software-only guys take a crack at digital design, look no further than Opencores

What books (if any) did you find helpful in learning about digital design? I'm currently reading Digital Design by M. Morris Mano.

-Chris

[olsenn]

What books (if any) did you find helpful in learning about digital design?

As I mentioned before: "Digital Design Using Digilent FPGA Boards"

This book covers all the basics of digital design from truth tables and Karnaugh maps, shows how to create more complex components (like binary counters, shift registers, flip-flops, etc) from the basic gates, and the shows how to implement said design in your choice of Verilog 2001 of VHDL.

[MacAttak]

The Xilinx ISE "WebPack edition" (the product from Xilinx that most closely approximates Quartus Web Edition) also has some annoying limits in the simulation engine that throttles it down severely once you cross a certain line of "user code" usage. It's a pretty low limit really, and while the simulator doesn't stop working entirely, it becomes immensely painful to use.

Are there any limitations like that in Quartus Web Edition?

[sci4me]

Okay, well I am currently attempting my first hello world program, fallowing the manual of course. I am getting an error when trying to use a pll. Here it is:

Code: [Select]

Error (176554): Can't place  PLL "pll:inst4|altpll:altpll_component|pll_altpll:auto_generated|pll1" -- I/O pin CLOCK_50 (port type INCLK of the PLL) is assigned to a location which is not connected to port type INCLK of any PLL on the device
Error (171000): Can't fit design in device
Error: Quartus II 64-Bit Fitter was unsuccessful. 2 errors, 3 warnings
Error: Peak virtual memory: 595 megabytes
Error: Processing ended: Fri Jul 26 15:08:19 2013
Error: Elapsed time: 00:00:04
Error: Total CPU time (on all processors): 00:00:04
Error (293001): Quartus II Full Compilation was unsuccessful. 4 errors, 4 warnings
Im fallowing the guide in the manual as closely as I can ... so, any ideas? I cant seem to figure it out.

[jahonen]

Okay, well I am currently attempting my first hello world program, fallowing the manual of course. I am getting an error when trying to use a pll. Here it is:

Code: [Select]

Error (176554): Can't place  PLL "pll:inst4|altpll:altpll_component|pll_altpll:auto_generated|pll1" -- I/O pin CLOCK_50 (port type INCLK of the PLL) is assigned to a location which is not connected to port type INCLK of any PLL on the device
Error (171000): Can't fit design in device
Error: Quartus II 64-Bit Fitter was unsuccessful. 2 errors, 3 warnings
Error: Peak virtual memory: 595 megabytes
Error: Processing ended: Fri Jul 26 15:08:19 2013
Error: Elapsed time: 00:00:04
Error: Total CPU time (on all processors): 00:00:04
Error (293001): Quartus II Full Compilation was unsuccessful. 4 errors, 4 warnings
Im fallowing the guide in the manual as closely as I can ... so, any ideas? I cant seem to figure it out.

Check the pin assignment of your clock input pin, it should be assigned to pin R8 (at least according to the schematic I found).

Regards,
Janne

[sci4me]

Its R8...

[sci4me]

Okay, turns out I had the wrong device selected. DERP! Now, I am trying to actually program my .sof onto my device and when I hit start, the progress bar immediately says failed... and nothing else happens... ideas?

Edit: Okay, I have been told to convert my sof to a jic and program with that. So, I converted it and tried programming with it, but nothing. It does the same thing.

Edit2: So, this error code 89... why isnt it documented? and if it is, why havent i found it yet? I found a single forum post on it but it was pretty useless. It told me to check the firewall settings for the jtag server... not sure what the hell thats supposed to mean on a linux computer (yes, i admit being a linux nub) so..

[sci4me]

I have made a post on the altera forum aswell, but so far, no luck. Im not really sure what to do... I mean I have made multiple designs I want to test out, but since I cant program the FPGA, they're just sitting there doing nothing... Somebody? I really want to get this working soon...

[marshallh]

It it says failed, it will always print status messages in the main window.
Go to the log and turn on the ALL filter to s how process messages. You should see something from Quartus II Programmer.

You just need a SOF to load the silicon. a JIC is basically what you would write to the NV config rom, along with a short loader stub that's run through jtag. You don't need it yet.

[sci4me]

Yeah, ive gotten this issue figured out. Now I need to figure out the pll thing.