PSoC combinational loop

[blueskull]

Is there any way to create an async SR latch inside a PSoC 4 device? Its macro library contains clocked SR latch, but I need an async one.
I created one with combination logic elements, but it shows the following warning.

Does it mean it have already broken the net for me (which is not what I intended to do), or it tells me that I should break the loop, but I have the discretion?

[danadak]

I had a problem where optimization would take out gates I wanted to stay, no warnings.
That was with all optimization off, at the time, ~ 3 years ago, no way to resolve the issue.

I would post this on Cypress.com PSOC forum, there may be a way to
defeat warning and make sure no nets are broken or to force particular
net routing.

Of course you could always eat a pin or two and route so tool does not know you
have latch loop........create the "net" externally.


Regards, Dana.

[Tainer]

I created one with combination logic elements

You could try making your own implementation in verilog