Queries on JTAG interface for a CPLD based system

[garvind25]

Hi,

I am trying to build a CPLD system which I plan to program using a JTAG parallel 3 cable. In the CPLD board design what should I connect for JTAG cable VCC supply? Since my board has 3.3v and 5.0v, I can use either. But the documentation https://www.xilinx.com/support/documentation/user_guides/xtp029.pdf] [url]https://www.xilinx.com/support/documentation/user_guides/xtp029.pdf [/url](page 4) says :

“ The VCC supply level must match the I/O voltage level of the FPGA slave-serial configuration pins for best signal integrity.”

Since my VCCIO of the CPLD is fixed to 3.3v for both banks, should I choose 3.3v. I am asking this because I have been using my JTAG parallel 3 cable with an FPGA system (Spartan 3 based) which provides 5 v supply to the cable.

Also, should I connect the pins of male JTAG port of the CPLD board directly to the respective pins or should I insert some resistance in-between the pins of the connector and IC? As per sheet 2 of link https://reference.digilentinc.com/_media/coolrunner-ii:coolrunner-ii_sch.pdf, they have inserted 200 ohms in each signal line and have also given pull up resistors for TMS and TDI. Why so, and how are these resistances being calculated pls?

Thanks and Regards,
Arvind Gupta
 

 

[rstofer]

The 200 ohm resistors are used to provide short circuit protection (and they slow down the edges).  The 10k resistors are chosen to provide adequate pull-up (which almost any value will do), not present much of a load to the programmer and not provide much of a voltage divider to the JTAG signals.  10k is just a common value.

If I couldn't figure out whether to use 3.3V or 5V for the JTAG programmer, I would put a voltage selector jumper near the JTAG connector.  Problem deferred...

[mikeselectricstuff]

The supply voltage to the cable is a supply for powering the cable, it's to tell the cable what voltage levels to use to talk to the device, so should match the I/O bank voltage