Question about the Lattice ICE40 MAC16 DSP cell

[hotwolf]

Hello,

I'm planning to do a hobby project using a Lattice ICE40 UltraPlus FPGA.  As I was reading through the documentation, I've noticed some odd logic in the block diagram of the MAC16 hard macro (pls. see attachment). The sum of the intermediate 8x8 products seems wrong when doing a 16 bit multiplication.

In my understanding the DSP cell should implement the following logic:

A[15:0] * B[15:0] =

((A[15:8] * 0x100) + A[7:0]) * ((B[15:8] * 0x100) + B[7:0]) =

(A[15:8] * B[15:8] * 0x10000) + (A[7:0] * B[15:8] * 0x100) + (A[15:8] * B[7:0] * 0x100) +  (A[7:0] * B[7:0]) =

          (F[15:0] * 0x10000) +          (J[15:0] * 0x100) +          (K[15:0] * 0x100) +           G[15:0]  =

(F[15:8] * 0x1000000) + ([F[7:0] + J[15:8] + K[15:8]) * 0x10000) + ((J[7:0] + K[7:0] + G[15:8]) * 0x100) + G[7:0]

However the block diagram suggests the following design implementation:

([F[7:0] + J[15:8]) * 0x1000000) + ((J[7:0] + K[15:8]) * 0x10000) + ((K[7:0] + G[15:8]) * 0x100) + G[7:0]

So I'm wondering, whether

• this is a documentation problem
• the design is broken
• my math is wrong

Is there anybody with hand-on experience on ICE40 FPGAs, who can confirm that the MAC16 cells do perform correct 16 bit multiplications?

Thanks,
Dirk

[daveshah]

I can confirm they function correctly in 16x16 mode. That diagram looks like a bit of a mess in terms of the adders after the multipliers. If you are curious, inside the simulation models in Radiant there are detailed verilog models for all parts of the MAC16.

[hotwolf]

Thanks for the confirmation. That is good to know.
I'll try to find the Verilog models.

Dirk

[iMo]

The IceCube2 and Radiant infer 16x16mult into the DSP module. I took the module's (SB_MAC16) wiring from there and put into IceStorm version of my design, works straight .
For example, outpC = inpA x inpB (unsigned):

Code: [Select]

SB_MAC16 my_16x16_mult (
    .A(inpA),
    .B(inpB),
    .C(16'h0000),
    .D(16'h0000),
    .O(outpC),
    .CLK(0),
    .CE(1),
    .IRSTTOP(0),
    .IRSTBOT(0),
    .ORSTTOP(0),
    .ORSTBOT(0),
    .AHOLD(1),
    .BHOLD(1),
    .CHOLD(0),
    .DHOLD(0),
    .OHOLDTOP(0),
    .OHOLDBOT(0),
    .OLOADTOP(0),
    .OLOADBOT(0),
    .ADDSUBTOP(0),
    .ADDSUBBOT(0),
    .CO(),
    .CI(0),
// MAC cascading ports
    .ACCUMCI(),
    .ACCUMCO(),
    .SIGNEXTIN(0),
    .SIGNEXTOUT()     );

defparam my_16x16_mult.B_SIGNED                            = 1'b0 ;
defparam my_16x16_mult.A_SIGNED                            = 1'b0 ;
defparam my_16x16_mult.BOTOUTPUT_SELECT                    = 2'b11 ;
defparam my_16x16_mult.TOPOUTPUT_SELECT                    = 2'b11 ;