Question regaRding SSRAM

[lawrence11]

Hello,

Here is an SSAM chip (Synchronous SRAM)

Why are all the pin address names just A,A,A,A....

I was expecting something along the lines of SRAM, A0,A1,A2,A3...etc...

What am I missing?

Thank you.

[ejeffrey]

The address lines are interchangeable.  You don't care what order your bits are physically on the chip, only that the data comes back when you apply the same address.

The low order bits A0 and A1 are significant as the chip can do a 4 word burst, and they are indicated specifically.

[lawrence11]

But I do care.

I wish to name them A0 TO A19 depending, the lowest Pin # with letter A is assigned A0,  the second lowest is assigned A1, and so on...

Same goes for DQx pins.

Can I work like this? And forget about this beeing a nameless chip and pretend it is like named and understandable SRAM?

Lets say I would burst write the fill 1M bits of X width, and after all, that I wanna address individually the 17th bit, I need a place where all my address pins will at some point go 00000000000000001001 (17).

At the start of the burst write operation, Do I have to preload the bits 0000 0000 0000 0000 0000 for it to start at zero and count 17 clock ticks to make the 17th write operation. Obviously the goal is to then find the correct bit #17 of X width according to my accounting.

Can I do this?

[ataradov]

Address is always pointing to a specific word (set of 18 or 36 bits in this case). When reading, as long as you apply the same address as you used for writing, you will get the same word back.

You can name them however you want, it won't make a difference.

But it is more convenient to route the board if you don't commit to specific indexes ahead of time.

Also, regular SRAM does not care about your addresses either. Manufacturers just name them according to JEDEC standard. But you can scramble them any way you like. In fact that's exactly what scrambling blocks do on secure processors.

[obiwanjacobi]

I have found that for sanity in debugging/developing hardware keeping the address pins 'lined up' saves a lot of head scratching. Principle of least surprise.

[2c]

[lawrence11]

Excuse me Ataradov,

But I am still confused,

I wish to know how the device knows that A0 pin is different then A14 pin. Both are not at all same value, one is worth 1, other is worth 16384.

If I first burst write in it and just preload it...

Basicly I need a 20bit binary counter when I am writing in it?

I thought that burst writing meant it did not need to be given 20bit address, just be told to start the the bottom first bit and fill up 1,2,3,4... etc... as the clock ticks.

However, When I wanna read from the device address 1 to 1000000, I wish to find the right data, and that is without me having to specify wich adddres bit is what pin wich if I start with first address 0000 0000 0000 0000 0000.

Do you understand my mindfuck?

[ataradov]

The deice only supports 4 word bursts, that's why A0 and A1 are explicitly numbered.

Quote from the DS:

This device integrates a 2-bit burst counter

[ataradov]

I don't see why not. The memory appears to be is fully pipelined, so you need to be prepared to deal with a couple clocks of latency, but you should get full 200/250 MHz throughput.

[lawrence11]

Dam Ataradov. you smart

I wish to be as smart as you pretty boy russian engineer.

Are you the guy who finished 1 hour before me on each exam?

Thanks tor informing me thusly.

[lawrence11]

Hey Ataradov, so if I just make my counter, I can just freely access my device and never go into burst mode?

This means I usE A0 To A19? And only A0 to A1 is of impotrance?

I am starting to get it now... Everything is scrambled anyways in an SRAM...

If I make my counter, reading device will also use this counter now since it is there.

I was gonna use only a reading counter ( from my microcontroller), the writing was just fast and sequential.

[Whales]

I wish to know how the device knows that A0 pin is different then A14 pin. Both are not at all same value, one is worth 1, other is worth 16384.

No, not at all.  The memory chip has no concept of numbers or sequence.  It's just a grid of cells.  The idea of '1-16383' is a completely human concept.

EDIT: I'm probably wrong, Atardov mentions pipelining.  Sounds like this memory has some optimisations that get ignored/wasted if you rearrange the lines?  Nonetheless what I write here holds for simpler SRAMS.

Every unique combination of inputs on the A pins points to a unique memory cell in the chip.

Here are a couple of mental exercises that might help. 


Wiring all the address lines Inverted

To simplify things I'm going to assume we're working with 8-bit addresses.

Let's invert every single address line before it gets to the SRAM chip.

   From          Inverter      SRAM
   circuit         Chip       inputs                     
                                             
     A0  --------> NOT ------>  A0
     A1  --------> NOT ------>  A1
     A2  --------> NOT ------>  A2
     A3  --------> NOT ------>  A3
     A4  --------> NOT ------>  A4
     A5  --------> NOT ------>  A5
     A6  --------> NOT ------>  A6
     A7  --------> NOT ------>  A7



This converts our addresses.  Eg:

  00000000 becomes 11111111
  00000001 becomes 11111110
  00000010 becomes 11111101
  00000011 becomes 11111100


Effectively we're inverting the address'.  new_address = totalmemsize - old_address

Let's walk through an example write and read:

(1) Our circuit tries to write to address 11100010.   In actual fact our number gets written to address 00011101 (the inverse).
(2) Our circuit tries to read from address 11100010.  In actual fact our number gets read from address 00011101 (the inverse).

We've written something to what we think is the correct address.  We've then read it back out again.  Nothing went wrong.  Our circuit is completely blind to the fact the memory chip is getting the 'wrong' addresses, because as far as it's concerned the promise of "one piece of data is stored at each unique address" is true.

Another example process: let's fill the first 100 bytes of memory, in order. 

(1) int i = 0;
(2) memory[ i ] = 6;
(3) if ( i >= 99 ) halt;
(4) i = i + 1;
(5) goto 1

What will actually happen is we will fill the last 100 cells of memory, in reverse order.  But we don't care how it's arranged inside the chip, all we care is that we can access it using address 0, 1, 2, 3, ..., 98, 99.

Substitution cipher

You may have tried one of these for fun some time in your life

A caeser cipher is a common example of a substitution cipher.  Read up on it if you're not familiar.

A proper substitution cipher can re-arrange the letters any way it wants.


The important thing to know about these ciphers: they are symmetrical.  That means if you perform operation X to convert your original message into the ciphered one, then you do the opposite of X to get it back again. 

Now for some mental stretches.

Let's pretend we have a chip that re-arranges our address lines in a pre-defined fashion.  Each line in is wired to a line out, and no wires are junctioned or missed:


   From          Re-arranger      SRAM
   circuit          Chip       inputs                     
                                             
     A0  -------->  #####  ------>  A0
     A1  -------->  #####  ------>  A1
     A2  -------->  #####  ------>  A2
     A3  -------->  #####  ------>  A3
     A4  -------->  #####  ------>  A4
     A5  -------->  #####  ------>  A5
     A6  -------->  #####  ------>  A6
     A7  -------->  #####  ------>  A7


Really we don't need a chip to do this.  Jumper wires would be fine.

What would happen if we used this circuit?  Again, everything would work fine.  Our SRAM would operate.  We'd be able to use all addresses of memory however we wanted and they would appear to work as normal.  Our circuit would be clueless to the fact its address lines are re-arranged. 

You can think of the re-arrange chip as a bit like a substitution cipher.  Even though the address lines only send data left to right in my diagram, let's pretend we can stand on either the circuit side or SRAM side at 'look' at the other.

When standing on the left (circuit) side and looking toward the right: our perception of reality will get re-arranged via process X.  If we draw picaso's face in the bits of the SRAM from here then our painted pixels will get re-arranged according to process X.

For us to see out painting: those pixels start on the right (SRAM) side and have to travel to the left.  They go through the inverse operation of X to do this.  By the time they reach our eyes they have been re-arranged into our original picture. 

Have I confused everyone enough yet?


The Exception

Has the memory chip been programmed by something else before we use it in our circuit?  We have to use the same wire order that it was programmed with, otherwise it will appear that the contents have been re-arranged.

Being an SRAM this isn't probably an issue

[ataradov]

Yes, you can just use all address lines in any order and never use burst mode.

[lawrence11]

Whales, you said something relevant, but for the rest, its ok... I seem to have evoked some very profound sentiment in you...

quote "I'm probably wrong, Atardov mentions pipelining.  Sounds like this memory has some optimisations that get ignored/wasted if you rearrange the lines?  Nonetheless what I write here holds for simpler SRAMS."

So I am guessing you did not read the document and going from intuition? I agree with you, I am also thinking the same... Can I really use it the way I think I can that fast if not using it in burst? I am not finding the answer easy to find. I dont see how a normal Asynch method gets slowed down from having that extra burst circuitry? I am confused since they dont say the contrary in an explicit way.

[Whales]

I seem to have evoked some very profound sentiment in you.

Hahaha.  I merely enjoy wiring things in strange ways to confuse my friends

So I am guessing you did not read the document and going from intuition?

Apologies, yes.  Make sure to check what I say makes sense in regards to the features of this chip and the datasheet. 

normal Asynch method gets slowed down from having that extra burst circuitry?

The datasheet mentions a mode pin that you have to set right to use the burst mode.  Presumably there will be different signal patterns and timings you are allowed to use depending on what mode you use the chip in.  (Apologies, have to go to bed, long trip tomorrow)

[ataradov]

This optimization seems to be only in burst.

What are you talking about? What optimization?

Even if you don't want to read the whole datasheet, it says right in the title "PIPELINE 'NO WAIT' STATE BUS SYNCHRONOUS SRAM".

What exactly in the datasheet makes you think that you can't read/write every clock cycle?

Pipelining has noting to do with arrangement of address lines. If you look at timing diagrams, there is a two clock cycle delay before data is read/needed for writing. But you can set a new address on every clock cycle. You just need to remember that corresponding data will need to be set two cock cycles later.

[ataradov]

All diagrams show two cycle latency, but the new address is presented on each cycle. Maybe you can screenshot some specific diagrams and highlight your concerns.

Someone is always going to have the best price.

But if you somehow believe that this chip will not work for you, then it is fine with me.