Red Pitaya, HD images for getting the schematic

[londondock]

Hi All,

Album of Red Pitaya HD images

Here's some images of the Red Pitaya, a 50 MHz scope, waveform generator, and generally re-programmable measurement tool, based on the Zynq ARM(2Cores)+FPGA combo chip. I was an initial backer of their Kickstarter, and the board actually works excellent with the apps the dev team has developed for it. The fact that you can now cram a scope, function gen, spectrum analyzer, etc., onto a credit card sized board with modern chips is kind of amazing, in my opinion.

However, I'm disappointed at the refusal to release full electrical schematics for the supposedly "open source" project. My guess is they want to keep imitators from generating similar products, as they have now partnered with RS/Allied to sell the board for ~$500.

Feel free to trace your own schematics for the sections you want from these images. I'm going to be working on this sporadically to completely reverse engineer the complete schematic, because Dave has inspired me with his recent video on rev. engineering the Rigol 1054Z input cans... 

Obviously, this is a lot of work, so if you want to help with that (divide up the work, etc), I'd be up for that.

[Palmitoxico]

I think that's impossible to reverse engineer it with only HD photos, this board surely has more than 2 layers and BGA stuff will make it even harder.

Isn't easier to project a whole new circuit than try to figure out all connections of this high density pcb?

[marshallh]

You will need to depopulate the pcb, mill and sand down the layers and image them separately.
My guess puts it at 8 layers

[londondock]

What do you mean by project a whole new circuit?

The board is indeed 8 layers, according to the transparent ladder diagram under the Ethernet jack.

I'm not planning on wrecking the board or sanding down the layers. Mainly I just plan overlaying via points, probing connections with a low voltage continuity tester, and then marking which points connect to each other.

Other things I've noticed so far:

-Not much in the way of input protection on SMA inputs/outputs. Only diode clamping in the amps/drivers really keeps it safe.

Lots of fast chips:
-AD8066, dual 145 MHz op amp on SMA-inputs
-LTC6200-10 165MHz, Rail-to-Rail op amps on SMA-outputs
-LTC6403, 200MHz, Low noise, low power fully differential input/output amp/driver for the main ADC

[marshallh]

You are not going to be able to fully reverse the pcb like that unless you can remove some BGAs. Maybe just reverse the parts that are interesting to you and that are accessible. (Most of the stuff will be boring/boilerplate hookups that you don't care about)

[londondock]

Yeah that's fair enough. Mostly I'm interested in the high speed input and output block diagrams.

Many of the BGA pin connections are listed in software header that's part of the Red Pitaya OS and base software headers. So there might be a little more to go on.

[tggzzz]

Thank you for you photos.

I concur with your belief that the principal benefit will be in understanding the i/o structures; complete reverse engineering is unnecessary.

I was particularly disappointed with the  implementation of the digital i/o on the E1/E2 connectors. IMNSHO they didn't have enough grounds, and they are not evenly distributed. In addition, the 3V3 i/o voltage precludes having differential input structures - and the replies to my questions didn't inspire confidence. FFI, see http://forum.redpitaya.com/viewtopic.php?f=9&t=32

I have not investigated "repurposing" the SATA connections for my ideas, since that would require deleting functional capability rather than adding to it.

[jboard146]

Get friendly with your dentist or vet. You need to get X-rays of the board.

Like others have posted it is 4+ layers.

[langwadt]

Thank you for you photos.

I concur with your belief that the principal benefit will be in understanding the i/o structures; complete reverse engineering is unnecessary.

I was particularly disappointed with the  implementation of the digital i/o on the E1/E2 connectors. IMNSHO they didn't have enough grounds, and they are not evenly distributed. In addition, the 3V3 i/o voltage precludes having differential input structures - and the replies to my questions didn't inspire confidence. FFI, see http://forum.redpitaya.com/viewtopic.php?f=9&t=32

I have not investigated "repurposing" the SATA connections for my ideas, since that would require deleting functional capability rather than adding to it.

runnning LVDS on Zynq with 3.3V IO is not a problem, just tell the tools you are running at 2.5V
 
if you turn on internal termination it'll be around 80R  instead of 100R but that's it

[tggzzz]

runnning LVDS on Zynq with 3.3V IO is not a problem, just tell the tools you are running at 2.5V
 
if you turn on internal termination it'll be around 80R  instead of 100R but that's it

Have you successfully done that on production equipment?

Why doesn't Xilinx indicate it is possible? Xilinx explicitly omit the possibility, thereby implying it is impermissable.

[langwadt]

runnning LVDS on Zynq with 3.3V IO is not a problem, just tell the tools you are running at 2.5V
 
if you turn on internal termination it'll be around 80R  instead of 100R but that's it

Have you successfully done that on production equipment?

Why doesn't Xilinx indicate it is possible? Xilinx explicitly omit the possibility, thereby implying it is impermissable.

I guess it may not be fully compliant LVDS that's why. I believe I saw it somewhere in a Xilinx
answer record

something like,

LVDS input always work, but you can't use termination, and you have to make sure the common mode
 with in range

LVDS OUTPUT/BIDIR, is not really supported because termination is always on, but it will probably work if you take into account the resulting termination value

if you set a port to CMOS25 and power it with 3.3V the drive levels will be higher which may or may not be a problem

[tggzzz]

runnning LVDS on Zynq with 3.3V IO is not a problem, just tell the tools you are running at 2.5V
 
if you turn on internal termination it'll be around 80R  instead of 100R but that's it

Have you successfully done that on production equipment?

Why doesn't Xilinx indicate it is possible? Xilinx explicitly omit the possibility, thereby implying it is impermissable.

I guess it may not be fully compliant LVDS that's why. I believe I saw it somewhere in a Xilinx
answer record

something like,

LVDS input always work, but you can't use termination, and you have to make sure the common mode
 with in range

LVDS OUTPUT/BIDIR, is not really supported because termination is always on, but it will probably work if you take into account the resulting termination value

if you set a port to CMOS25 and power it with 3.3V the drive levels will be higher which may or may not be a problem

So, it might work. Or it might not work. Or it might work when the pattern is right. Or it might work for a while, until the overstressed i/o block subtly degrades.

When I'm pushing technology trying to get a 1or 2Gb/s signal into a device, I don't want to have to fight unknown and unalterable and uncircumventable behaviour.

[miguelvp]

The datasheet has 35 references about LVDS

http://www.xilinx.com/support/documentation/data_sheets/ds187-XC7Z010-XC7Z020-Data-Sheet.pdf

GPIOs usually support LVDS unless the datasheet stipulates that you should only use certain pins for certain functions (like JTAG for example)

To the OP, are you aware of this link:
http://wiki.redpitaya.com/index.php

GPIO16 module schematic:
https://www.dropbox.com/s/h4hmabxlf5xw7g4/Schematic_GPIO16_A_InformativeOnly.pdf

Also if you need to drive HDMI or longer drives where LVDS is not enough, then there is some paper somewhere on how to convert LVDS to TMDS. I did link it at a time a while ago. I'll do a search to see if I can find it.

Edit: Found it
http://m.eet.com/media/1135468/330072.pdf

[langwadt]

runnning LVDS on Zynq with 3.3V IO is not a problem, just tell the tools you are running at 2.5V
 
if you turn on internal termination it'll be around 80R  instead of 100R but that's it

Have you successfully done that on production equipment?

Why doesn't Xilinx indicate it is possible? Xilinx explicitly omit the possibility, thereby implying it is impermissable.

I guess it may not be fully compliant LVDS that's why. I believe I saw it somewhere in a Xilinx
answer record

something like,

LVDS input always work, but you can't use termination, and you have to make sure the common mode
 with in range

LVDS OUTPUT/BIDIR, is not really supported because termination is always on, but it will probably work if you take into account the resulting termination value

if you set a port to CMOS25 and power it with 3.3V the drive levels will be higher which may or may not be a problem

So, it might work. Or it might not work. Or it might work when the pattern is right. Or it might work for a while, until the overstressed i/o block subtly degrades.

When I'm pushing technology trying to get a 1or 2Gb/s signal into a device, I don't want to have to fight unknown and unalterable and uncircumventable behaviour.

afair the minimum pulse width limits you to  ~350MHz on the Zynq

Input always works, you just have to use external termination if you don't use 2.5V

Powering a bank with a different voltage than you set it for will not damage anything,
but it the drive levels, fast/slow slew etc. might change so you IBIS simulations if you do
those will not be correct

[tggzzz]

runnning LVDS on Zynq with 3.3V IO is not a problem, just tell the tools you are running at 2.5V
 
if you turn on internal termination it'll be around 80R  instead of 100R but that's it

Have you successfully done that on production equipment?

Why doesn't Xilinx indicate it is possible? Xilinx explicitly omit the possibility, thereby implying it is impermissable.

I guess it may not be fully compliant LVDS that's why. I believe I saw it somewhere in a Xilinx
answer record

something like,

LVDS input always work, but you can't use termination, and you have to make sure the common mode
 with in range

LVDS OUTPUT/BIDIR, is not really supported because termination is always on, but it will probably work if you take into account the resulting termination value

if you set a port to CMOS25 and power it with 3.3V the drive levels will be higher which may or may not be a problem

So, it might work. Or it might not work. Or it might work when the pattern is right. Or it might work for a while, until the overstressed i/o block subtly degrades.

When I'm pushing technology trying to get a 1or 2Gb/s signal into a device, I don't want to have to fight unknown and unalterable and uncircumventable behaviour.

afair the minimum pulse width limits you to  ~350MHz on the Zynq

Are you referring to a clock signal, because I wasn't - consider SERDES. If you weren't, then I would be very interested in knowing the source of that information.

Input always works, you just have to use external termination if you don't use 2.5V

RedPitaya doesn't have any termination on the relevant lines, so it would be pattern sensitive. No point in adding off-board termination since the stub length is too long.

Powering a bank with a different voltage than you set it for will not damage anything,
but it the drive levels, fast/slow slew etc. might change so you IBIS simulations if you do
those will not be correct

IBIS won't tell you anything about damage - and neither does Xilinx. I'm not going to risk basing a design on unsupported guesses - there's too much scope for very late unpleasant surprises.

[miguelvp]

I have no experience with xilinx other than I'm waiting for the Papilio Duo then I guess I'll dive into it but Altera has no trouble with LVDS signals,and the Red Pitaya does seem to have 8 available differential pairs in one of the connectors

If limited to ~350 MHz there is no reason you couldn't use multiple pairs.

[tggzzz]

The datasheet has 35 references about LVDS

http://www.xilinx.com/support/documentation/data_sheets/ds187-XC7Z010-XC7Z020-Data-Sheet.pdf

GPIOs usually support LVDS unless the datasheet stipulates that you should only use certain pins for certain functions (like JTAG for example)

Which LVDS i/o structures can be used with the 3.3V supply in the Red Pitaya?

Only one differential i/o structure can be used, TMDS - which is only for video signals.

GPIO16 module schematic:
https://www.dropbox.com/s/h4hmabxlf5xw7g4/Schematic_GPIO16_A_InformativeOnly.pdf

Helpful.

I believe, without checking, that CN2 is the digital connector in question. It has 6 unconnected pins, 7 differential (14 single-ended) signals, but only 2 gnd pins and 2 3V3 pins at the end of the connector.  IMNSHO and without knowing the constraints on the board, it would have been preferable and possible to have 8 gnd pins distributed amongst the 14 signal lines. That would improve the signal integrity for high speed digital signals.

Also if you need to drive HDMI or longer drives where LVDS is not enough, then there is some paper somewhere on how to convert LVDS to TMDS. I did link it at a time a while ago. I'll do a search to see if I can find it.

Edit: Found it
http://m.eet.com/media/1135468/330072.pdf

Interesting, but unhelpful since it requires 50ohm terminations at the receiver - which are not present on the Red Pitaya board (quite reasonably since they aren't required for most i/o standards).

[miguelvp]

So you can't put a 100 Ohm resistor across the pin pair?
Also they support TMDS according to the datasheet I linked before.
Edit: among other differential signaling that they support, it's in the datasheet.

Maybe this will help as well as in what SelectIO resources are available (link comes from the mentioned datasheet).

http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

Edit, but what do I know, I only looked into this for less than 15 minutes total.
Some other relevant links

Implementation of a FPGA-based Interface to a High Speed Image Sensor
http://d-nb.info/1057871729/34

LVDS Display controller for microprocessors (using spartan though)
http://blog.tkjelectronics.dk/2012/10/lvds-display-controller-for-microprocessors/

Max10 (Altera) but I got an eval board for $30 so good to know it can handle it.
http://www.altera.com/literature/hb/max-10/ug_m10_lvds.pdf

Edit 2: Also I don't know how the board is done so I guess it's valid to assume the traces are not length matched.

[tggzzz]

I have no experience with xilinx other than I'm waiting for the Papilio Duo then I guess I'll dive into it but Altera has no trouble with LVDS signals,and the Red Pitaya does seem to have 8 available differential pairs in one of the connectors

Please note the other points I have made about signal integrity w.r.t. terminations and insufficient poorly-distributed GND pins.

If limited to ~350 MHz there is no reason you couldn't use multiple pairs.

Yes, there is a reason I can't. My interest is in a signal that is inherently a 1Gb/s, preferably 2Gb/s single serial IO line. It will be parallelised inside the FPGA using SERDES I/O structure.

[tggzzz]

So you can't put a 100 Ohm resistor across the pin pair?

Not at the receiver, no. Somewhere away from the receiver, yes - but that's useless w.r.t. signal integrity.

Edit, but what do I know, I only looked into this for less than 15 minutes total.

Yes, I can tell, but thanks for making it explicit. I have looked at it for far longer.

I welcome specific examples of how to get a serial LVDS 1 or 2Gb/s signal into the Red Pitaya FPGA, given the Red Pitaya's implementation w.r.t. I/O voltage and lack of ground pins on the connector.

[miguelvp]

I guess you read both the datasheet and the Select IO app notes then.

Here is a 1050 Mb/s example (spartan 6)
http://www.xilinx.com/support/documentation/application_notes/xapp1064.pdf
Although that app note uses a clock of 150MHz so it requires the PLL and BUFPLL to run with a 7 multiplier to get to 1050MHz.

But since you are all convinced that you need ground pins on the connector for differential pair transmission then I don't know what else to say, Cat-6 is not affected by the lack of grounds around the signals.

[miguelvp]

Diff signals supported by the Zynq

Note the link about more information, that would be the other app note that I linked, and maybe you can even look for internal terminations while you are at it (meaning inside the FPGA)
Nope, the FPGA diff pins don't have enough grounds in between either for your signal integrity.

[alex.forencich]

You are not going to be able to fully reverse the pcb like that unless you can remove some BGAs. Maybe just reverse the parts that are interesting to you and that are accessible. (Most of the stuff will be boring/boilerplate hookups that you don't care about)

I don't think that's entirely true.  There are solutions (ftjrev) for probing JTAG accessible devices.  As long as you can get access to the other end of the trace, you can figure out what pin it is connected to.  The DRAM chip will be connected to standard pins due to the onboard memory controller - consult the pinouts for the FPGA and it should be obvious.  Looks like the only BGA parts on the board are the FPGA and the DRAM, so it should be possible to back out most of a netlist without too much trouble.  Figuring out what all the passives are will be a more annoying problem, though. 

[londondock]

You are not going to be able to fully reverse the pcb like that unless you can remove some BGAs. Maybe just reverse the parts that are interesting to you and that are accessible. (Most of the stuff will be boring/boilerplate hookups that you don't care about)

I don't think that's entirely true.  There are solutions (ftjrev) for probing JTAG accessible devices.  As long as you can get access to the other end of the trace, you can figure out what pin it is connected to.  The DRAM chip will be connected to standard pins due to the onboard memory controller - consult the pinouts for the FPGA and it should be obvious.  Looks like the only BGA parts on the board are the FPGA and the DRAM, so it should be possible to back out most of a netlist without too much trouble.  Figuring out what all the passives are will be a more annoying problem, though.

Thanks Alex, that's basically what I was thinking. It's not like there are components hidden inside the PCB, so all parts that have solder exposed pins could be probed/traced back with a multimeter. Don't really need perfect values for all passives to get the general idea of what is going on with input/output blocks.

As an example, my first section was just to see how they have implemented the IN1 and IN2 input stages, with the jumpers for "low" and "high" voltage signals. Picture is attached.

After the AD8066 op amp, there is a bunch of surface mount inductors before the LTC6403 driver. I've not done much RF design work myself, so I find it interesting how they basically get good (ie. flat or nearly so) response up to the claimed bandwidth of 50 MHz with lumped element SMD chips placed on these tiny traces. I just figured all RF boards were controlled impedance microstrips, etc., but I've only been doing electronics as a hobby for about 3 years now. I guess you just need to know your amps/passive components SPICE models/parameters and model away?

[alex.forencich]

You are not going to be able to fully reverse the pcb like that unless you can remove some BGAs. Maybe just reverse the parts that are interesting to you and that are accessible. (Most of the stuff will be boring/boilerplate hookups that you don't care about)

I don't think that's entirely true.  There are solutions (ftjrev) for probing JTAG accessible devices.  As long as you can get access to the other end of the trace, you can figure out what pin it is connected to.  The DRAM chip will be connected to standard pins due to the onboard memory controller - consult the pinouts for the FPGA and it should be obvious.  Looks like the only BGA parts on the board are the FPGA and the DRAM, so it should be possible to back out most of a netlist without too much trouble.  Figuring out what all the passives are will be a more annoying problem, though.

Thanks Alex, that's basically what I was thinking. It's not like there are components hidden inside the PCB, so all parts that have solder exposed pins could be probed/traced back with a multimeter. Don't really need perfect values for all passives to get the general idea of what is going on with input/output blocks.

As an example, my first section was just to see how they have implemented the IN1 and IN2 input stages, with the jumpers for "low" and "high" voltage signals. Picture is attached.

After the AD8066 op amp, there is a bunch of surface mount inductors before the LTC6403 driver. I've not done much RF design work myself, so I find it interesting how they basically get good (ie. flat or nearly so) response up to the claimed bandwidth of 50 MHz with lumped element SMD chips placed on these tiny traces. I just figured all RF boards were controlled impedance microstrips, etc., but I've only been doing electronics as a hobby for about 3 years now. I guess you just need to know your amps/passive components SPICE models/parameters and model away?

50 MHz is not so bad.  The wavelength in the air at 50 MHz is 6 meters, so basically anything that you can stick in a box that sits on your desk is going to be lumped element, much less stuff on one board.  5 GHz, on the other hand, has a wavelength of 6 cm, so distributed effects are much more pronounced.  It gets really fun as you start getting up there - for example, 50 GHz has a wavelength of 6 mm, so you would get a significant phase shift going through an 0402 SMD component! 

[awallin]

FWIW, here's a Zynq-board that has published schematics and layout (KiCAD files should be on github):
http://www.parallella.org/board/
I wouldn't be at all surprised if many of the early Zynq dev-boards are copy/paste clones of some Xilinx reference design and/or clones of eachother.

[tggzzz]

Here is a 1050 Mb/s example (spartan 6)
http://www.xilinx.com/support/documentation/application_notes/xapp1064.pdf
Although that app note uses a clock of 150MHz so it requires the PLL and BUFPLL to run with a 7 multiplier to get to 1050MHz.

I believe I may have two tricks up my sleeve, but I haven't proved either by implementation; hence my statement "1 or 2GB/s".

But since you are all convinced that you need ground pins on the connector for differential pair transmission then I don't know what else to say, Cat-6 is not affected by the lack of grounds around the signals.

One counter-example in a completely different and very specific application is a poor counterweight to standard generally applicable theory and practice.

[tggzzz]

Diff signals supported by the Zynq

Note the link about more information, that would be the other app note that I linked, and maybe you can even look for internal terminations while you are at it (meaning inside the FPGA)

Oh, please read what I have written, and stop wasting your time by posting irrelevant details. Your guesses w.r.t. FPGAs you haven't used embedded in boards you haven't looked at are less than impressive.

The Red Pitaya board has 3V3 i/o. As I noted that removes all possibilities except TMDS - and most signal sources aren't TMDS (PECL or LVDS are much more common).

Nope, the FPGA diff pins don't have enough grounds in between either for your signal integrity.

Clearly you haven't got a clue what does and doesn't affect w.r.t. signal integrity.

I suggest that before you attempt to implement any medium speed (i.e. Gb/s) digital board you read, learn and inwardly digest the theory and praxis of signal transmission. A good starting point is http://www.sigcon.com/Pubs/pubsKeyword.htm

[tggzzz]

50 MHz is not so bad.  The wavelength in the air at 50 MHz is 6 meters, so basically anything that you can stick in a box that sits on your desk is going to be lumped element, much less stuff on one board.  5 GHz, on the other hand, has a wavelength of 6 cm, so distributed effects are much more pronounced.  It gets really fun as you start getting up there - for example, 50 GHz has a wavelength of 6 mm, so you would get a significant phase shift going through an 0402 SMD component!

Oh, 50GHz is worse than that! You can get significant phase shifts inside the transistors themselves, which limits the size of the active areas. When coupled with the power dissipation inside the active area, the maximum power output is significantly limited.

Unfortunately it has been 18 years since I was in the area, so I forget the actual power limit. However it was a significant limitation on the range of radio systems. Positives are that high gain antennas are very compact, and anti-reflection coatings (like the bloom on camera lenses) are practical and beneficial.

[miguelvp]

It will be a better approach to know what high speed differential protocol you have in mind that uses 3.3 volts and it's not TMDS, and why TMDS is out of the question or lower voltages protocols are out as well?

Just because it does provide 3.3V I/O it doesn't mean it only supports 3.3V I/O.

Another thing I don't get from your claims about ground pins is that, isn't it the whole purpose of using differential pair communication to keep integrity even if the ground level changes? therefore eliminating ground bounce?

[tggzzz]

It will be a better approach to know what high speed differential protocol you have in mind that uses 3.3 volts and it's not TMDS, and why TMDS is out of the question or lower voltages protocols are out as well?

As I have noted previously, the devices I have to use are LVDS or conceivably PECL levels (and are DC-to-daylight without any coding).

Just because it does provide 3.3V I/O it doesn't mean it only supports 3.3V I/O.

"It" is ambiguous in that statement. This thread is only about the Red Pitaya.

Another thing I don't get from your claims about ground pins is that, isn't it the whole purpose of using differential pair communication to keep integrity even if the ground level changes? therefore eliminating ground bounce?

No.

Differential pairs help reduce ground bounce at the transmitter, but that's only a small part of their benefit. Other benefits include reduced EMI generation, reduced susceptibility to EMI, noise immunity, and - provided there are high quality transmission lines - signal integrity.

As I noted before, you really will benefit from understanding the content at http://www.sigcon.com/Pubs/pubsKeyword.htm Similar content has been available for since the 1970s from all the major digital IC manufacturers, but that site collates the information in one place. Originally the issues were only really relevant for 10K/100K ECL, but since then the same issues have become relevant to most digital technologies.

[free_electron]

500$ ? trashcan open , -shove- , trashcan close.

for 500$ i can get a real scope and a real signal generator instead of this kludge that can't even use normal scope probes , can't detect attenuation , has limited input range , no kind of bulletproofing like real scope input circuitry.

no thanks.

[miguelvp]

Now with 5 V requirments and operational between 1GHz to 2GHz you might be asking too much of a cheap FPGA with a SoC built in.

High speed transceivers are available for the XC7Z015 only not available on the XC7Z010.
Also I did notice their connectors on the usermanual and they have the positive and negative of the signals across each other, so forget about length matching since the external pin is going to have a longer trace than the internal one.

For differential comunications you want them side to side and alternating form edge to edge, so you'll need to add lenght to one of the traces.

LVDS 2.5 V is compatible with LVDS 3.3V and with LVPECL. Otherwise the full Xilinx 7 series would be worthless.

The i/o pins on the Zynq are not restricted to only 3.3V (well, they are fixed to 3.3V on bank 34 but the diff pins are on bank 35)

Or is there something that I'm missing, that prevents you to set the full 35 bank to say 2.5V to do LVDS_25?

If everything else fails, then use the Gigabit Ethernet for communications, or make your own LVDS daughter board with the proper voltages and terminations.

[tggzzz]

Now with 5 V requirments and operational between 1GHz to 2GHz you might be asking too much of a cheap FPGA with a SoC built in.

High speed transceivers are available for the XC7Z015 only not available on the XC7Z010.
Also I did notice their connectors on the usermanual and they have the positive and negative of the signals across each other, so forget about length matching since the external pin is going to have a longer trace than the internal one.

For differential comunications you want them side to side and alternating form edge to edge, so you'll need to add lenght to one of the traces.

LVDS 2.5 V is compatible with LVDS 3.3V and with LVPECL. Otherwise the full Xilinx 7 series would be worthless.

The i/o pins on the Zynq are not restricted to only 3.3V (well, they are fixed to 3.3V on bank 34 but the diff pins are on bank 35)

Or is there something that I'm missing, that prevents you to set the full 35 bank to say 2.5V to do LVDS_25?

If everything else fails, then use the Gigabit Ethernet for communications, or make your own LVDS daughter board with the proper voltages and terminations.

Yes, you are missing three things:

• a basic comprehension that Red Pitaya has made design choices - and that they aren't evident in any Xilinx data sheet or app note
• a basic understanding of signal integrity of medium speed digital signals - despite having been pointed in a direction for you to start learning about it 
• imagination of how to use a part in novel ways that still meet the device's specifications - unsurprising since you don't know my objectives

[langwadt]

So you can't put a 100 Ohm resistor across the pin pair?

Not at the receiver, no. Somewhere away from the receiver, yes - but that's useless w.r.t. signal integrity.

Edit, but what do I know, I only looked into this for less than 15 minutes total.

Yes, I can tell, but thanks for making it explicit. I have looked at it for far longer.

I welcome specific examples of how to get a serial LVDS 1 or 2Gb/s signal into the Red Pitaya FPGA, given the Red Pitaya's implementation w.r.t. I/O voltage and lack of ground pins on the connector.

The lack of grounds is a problem if you want to use a cable, if you plug in a board you'll have to measure it to see how much of an impedance bump you get, at GB speeds the choice of connector is probably a bigger problem

Receiving LVDS, with an input configured for LVDS25 and powered by 3.3V is not a problem, the only issue in the internal termination that according to Xilinx will be ~80R, but the LVDS specification already have something like +/-20% spec on termination so the transmission line should just be designed for 80R instead of 100R

anywho, just get a microzed instead, the connectors are much better for high speed, have proper grounding, it looks each pair is matched length and it is less than half the price

[langwadt]

I guess you read both the datasheet and the Select IO app notes then.

Here is a 1050 Mb/s example (spartan 6)
http://www.xilinx.com/support/documentation/application_notes/xapp1064.pdf
Although that app note uses a clock of 150MHz so it requires the PLL and BUFPLL to run with a 7 multiplier to get to 1050MHz.

But since you are all convinced that you need ground pins on the connector for differential pair transmission then I don't know what else to say, Cat-6 is not affected by the lack of grounds around the signals.

cat6 is twisted, when you don't have twisted pairs you get different loading on each wire in the pair depending on what goes on the the adjacent channels

[tggzzz]

I welcome specific examples of how to get a serial LVDS 1 or 2Gb/s signal into the Red Pitaya FPGA, given the Red Pitaya's implementation w.r.t. I/O voltage and lack of ground pins on the connector.

The lack of grounds is a problem if you want to use a cable, if you plug in a board you'll have to measure it to see how much of an impedance bump you get, at GB speeds the choice of connector is probably a bigger problem

I don't have any suitable equipment to do that. I agree the connector certainly isn't ideal, but if everything else looked good it might have been worth taking a punt on a Pitaya.

Receiving LVDS, with an input configured for LVDS25 and powered by 3.3V is not a problem, the only issue in the internal termination that according to Xilinx will be ~80R, but the LVDS specification already have something like +/-20% spec on termination so the transmission line should just be designed for 80R instead of 100R

I haven't seen any source of information to that effect; what's the basis for those statements? I'm particularly curious as to why the termination would be 20% lower.

anywho, just get a microzed instead, the connectors are much better for high speed, have proper grounding, it looks each pair is matched length and it is less than half the price

Ah, just so. I'm ahead of you there - I already have a MicroZed as my primary development platform! It is a nice little board with all those advantages and more. There's also a small eco-system with several MicroZed variants and carrier boards. There are, of course, other similar boards from other manufacturers, albeit more expensive.

The advantage of a Red Pitaya is simply that it is "out there in the wild", with ADCs/scope, and with potentially a different ecosystem. That would be "nice to have" but definitely not "compelling".

[GermanMarkus]

Hey guys,
I´m not sure if this is still interesting for someone, but there is a link from RedPitaya to some development schematics:
http://wiki.redpitaya.com/index.php?title=Red_Pitaya_Board_HW_Schematics