Red Pitaya, HD images for getting the schematic

[awallin]

FWIW, here's a Zynq-board that has published schematics and layout (KiCAD files should be on github):
http://www.parallella.org/board/
I wouldn't be at all surprised if many of the early Zynq dev-boards are copy/paste clones of some Xilinx reference design and/or clones of eachother.

[tggzzz]

Here is a 1050 Mb/s example (spartan 6)
http://www.xilinx.com/support/documentation/application_notes/xapp1064.pdf
Although that app note uses a clock of 150MHz so it requires the PLL and BUFPLL to run with a 7 multiplier to get to 1050MHz.

I believe I may have two tricks up my sleeve, but I haven't proved either by implementation; hence my statement "1 or 2GB/s".

But since you are all convinced that you need ground pins on the connector for differential pair transmission then I don't know what else to say, Cat-6 is not affected by the lack of grounds around the signals.

One counter-example in a completely different and very specific application is a poor counterweight to standard generally applicable theory and practice.

[tggzzz]

Diff signals supported by the Zynq

Note the link about more information, that would be the other app note that I linked, and maybe you can even look for internal terminations while you are at it (meaning inside the FPGA)

Oh, please read what I have written, and stop wasting your time by posting irrelevant details. Your guesses w.r.t. FPGAs you haven't used embedded in boards you haven't looked at are less than impressive.

The Red Pitaya board has 3V3 i/o. As I noted that removes all possibilities except TMDS - and most signal sources aren't TMDS (PECL or LVDS are much more common).

Nope, the FPGA diff pins don't have enough grounds in between either for your signal integrity.

Clearly you haven't got a clue what does and doesn't affect w.r.t. signal integrity.

I suggest that before you attempt to implement any medium speed (i.e. Gb/s) digital board you read, learn and inwardly digest the theory and praxis of signal transmission. A good starting point is http://www.sigcon.com/Pubs/pubsKeyword.htm

[tggzzz]

50 MHz is not so bad.  The wavelength in the air at 50 MHz is 6 meters, so basically anything that you can stick in a box that sits on your desk is going to be lumped element, much less stuff on one board.  5 GHz, on the other hand, has a wavelength of 6 cm, so distributed effects are much more pronounced.  It gets really fun as you start getting up there - for example, 50 GHz has a wavelength of 6 mm, so you would get a significant phase shift going through an 0402 SMD component!

Oh, 50GHz is worse than that! You can get significant phase shifts inside the transistors themselves, which limits the size of the active areas. When coupled with the power dissipation inside the active area, the maximum power output is significantly limited.

Unfortunately it has been 18 years since I was in the area, so I forget the actual power limit. However it was a significant limitation on the range of radio systems. Positives are that high gain antennas are very compact, and anti-reflection coatings (like the bloom on camera lenses) are practical and beneficial.

[miguelvp]

It will be a better approach to know what high speed differential protocol you have in mind that uses 3.3 volts and it's not TMDS, and why TMDS is out of the question or lower voltages protocols are out as well?

Just because it does provide 3.3V I/O it doesn't mean it only supports 3.3V I/O.

Another thing I don't get from your claims about ground pins is that, isn't it the whole purpose of using differential pair communication to keep integrity even if the ground level changes? therefore eliminating ground bounce?

[tggzzz]

It will be a better approach to know what high speed differential protocol you have in mind that uses 3.3 volts and it's not TMDS, and why TMDS is out of the question or lower voltages protocols are out as well?

As I have noted previously, the devices I have to use are LVDS or conceivably PECL levels (and are DC-to-daylight without any coding).

Just because it does provide 3.3V I/O it doesn't mean it only supports 3.3V I/O.

"It" is ambiguous in that statement. This thread is only about the Red Pitaya.

Another thing I don't get from your claims about ground pins is that, isn't it the whole purpose of using differential pair communication to keep integrity even if the ground level changes? therefore eliminating ground bounce?

No.

Differential pairs help reduce ground bounce at the transmitter, but that's only a small part of their benefit. Other benefits include reduced EMI generation, reduced susceptibility to EMI, noise immunity, and - provided there are high quality transmission lines - signal integrity.

As I noted before, you really will benefit from understanding the content at http://www.sigcon.com/Pubs/pubsKeyword.htm Similar content has been available for since the 1970s from all the major digital IC manufacturers, but that site collates the information in one place. Originally the issues were only really relevant for 10K/100K ECL, but since then the same issues have become relevant to most digital technologies.

[free_electron]

500$ ? trashcan open , -shove- , trashcan close.

for 500$ i can get a real scope and a real signal generator instead of this kludge that can't even use normal scope probes , can't detect attenuation , has limited input range , no kind of bulletproofing like real scope input circuitry.

no thanks.

[miguelvp]

Now with 5 V requirments and operational between 1GHz to 2GHz you might be asking too much of a cheap FPGA with a SoC built in.

High speed transceivers are available for the XC7Z015 only not available on the XC7Z010.
Also I did notice their connectors on the usermanual and they have the positive and negative of the signals across each other, so forget about length matching since the external pin is going to have a longer trace than the internal one.

For differential comunications you want them side to side and alternating form edge to edge, so you'll need to add lenght to one of the traces.

LVDS 2.5 V is compatible with LVDS 3.3V and with LVPECL. Otherwise the full Xilinx 7 series would be worthless.

The i/o pins on the Zynq are not restricted to only 3.3V (well, they are fixed to 3.3V on bank 34 but the diff pins are on bank 35)

Or is there something that I'm missing, that prevents you to set the full 35 bank to say 2.5V to do LVDS_25?

If everything else fails, then use the Gigabit Ethernet for communications, or make your own LVDS daughter board with the proper voltages and terminations.

[tggzzz]

Now with 5 V requirments and operational between 1GHz to 2GHz you might be asking too much of a cheap FPGA with a SoC built in.

High speed transceivers are available for the XC7Z015 only not available on the XC7Z010.
Also I did notice their connectors on the usermanual and they have the positive and negative of the signals across each other, so forget about length matching since the external pin is going to have a longer trace than the internal one.

For differential comunications you want them side to side and alternating form edge to edge, so you'll need to add lenght to one of the traces.

LVDS 2.5 V is compatible with LVDS 3.3V and with LVPECL. Otherwise the full Xilinx 7 series would be worthless.

The i/o pins on the Zynq are not restricted to only 3.3V (well, they are fixed to 3.3V on bank 34 but the diff pins are on bank 35)

Or is there something that I'm missing, that prevents you to set the full 35 bank to say 2.5V to do LVDS_25?

If everything else fails, then use the Gigabit Ethernet for communications, or make your own LVDS daughter board with the proper voltages and terminations.

Yes, you are missing three things:

• a basic comprehension that Red Pitaya has made design choices - and that they aren't evident in any Xilinx data sheet or app note
• a basic understanding of signal integrity of medium speed digital signals - despite having been pointed in a direction for you to start learning about it 
• imagination of how to use a part in novel ways that still meet the device's specifications - unsurprising since you don't know my objectives

[langwadt]

So you can't put a 100 Ohm resistor across the pin pair?

Not at the receiver, no. Somewhere away from the receiver, yes - but that's useless w.r.t. signal integrity.

Edit, but what do I know, I only looked into this for less than 15 minutes total.

Yes, I can tell, but thanks for making it explicit. I have looked at it for far longer.

I welcome specific examples of how to get a serial LVDS 1 or 2Gb/s signal into the Red Pitaya FPGA, given the Red Pitaya's implementation w.r.t. I/O voltage and lack of ground pins on the connector.

The lack of grounds is a problem if you want to use a cable, if you plug in a board you'll have to measure it to see how much of an impedance bump you get, at GB speeds the choice of connector is probably a bigger problem

Receiving LVDS, with an input configured for LVDS25 and powered by 3.3V is not a problem, the only issue in the internal termination that according to Xilinx will be ~80R, but the LVDS specification already have something like +/-20% spec on termination so the transmission line should just be designed for 80R instead of 100R

anywho, just get a microzed instead, the connectors are much better for high speed, have proper grounding, it looks each pair is matched length and it is less than half the price

[langwadt]

I guess you read both the datasheet and the Select IO app notes then.

Here is a 1050 Mb/s example (spartan 6)
http://www.xilinx.com/support/documentation/application_notes/xapp1064.pdf
Although that app note uses a clock of 150MHz so it requires the PLL and BUFPLL to run with a 7 multiplier to get to 1050MHz.

But since you are all convinced that you need ground pins on the connector for differential pair transmission then I don't know what else to say, Cat-6 is not affected by the lack of grounds around the signals.

cat6 is twisted, when you don't have twisted pairs you get different loading on each wire in the pair depending on what goes on the the adjacent channels

[tggzzz]

I welcome specific examples of how to get a serial LVDS 1 or 2Gb/s signal into the Red Pitaya FPGA, given the Red Pitaya's implementation w.r.t. I/O voltage and lack of ground pins on the connector.

The lack of grounds is a problem if you want to use a cable, if you plug in a board you'll have to measure it to see how much of an impedance bump you get, at GB speeds the choice of connector is probably a bigger problem

I don't have any suitable equipment to do that. I agree the connector certainly isn't ideal, but if everything else looked good it might have been worth taking a punt on a Pitaya.

Receiving LVDS, with an input configured for LVDS25 and powered by 3.3V is not a problem, the only issue in the internal termination that according to Xilinx will be ~80R, but the LVDS specification already have something like +/-20% spec on termination so the transmission line should just be designed for 80R instead of 100R

I haven't seen any source of information to that effect; what's the basis for those statements? I'm particularly curious as to why the termination would be 20% lower.

anywho, just get a microzed instead, the connectors are much better for high speed, have proper grounding, it looks each pair is matched length and it is less than half the price

Ah, just so. I'm ahead of you there - I already have a MicroZed as my primary development platform! It is a nice little board with all those advantages and more. There's also a small eco-system with several MicroZed variants and carrier boards. There are, of course, other similar boards from other manufacturers, albeit more expensive.

The advantage of a Red Pitaya is simply that it is "out there in the wild", with ADCs/scope, and with potentially a different ecosystem. That would be "nice to have" but definitely not "compelling".

[GermanMarkus]

Hey guys,
I´m not sure if this is still interesting for someone, but there is a link from RedPitaya to some development schematics:
http://wiki.redpitaya.com/index.php?title=Red_Pitaya_Board_HW_Schematics