Reducing Phase Noise

[aep9690]

I am working on a project with a very low current requirement.  Right now its mostly working but I have a problem where my 32MHz oscillator has too much phase noise which causes measurement error with my microcontrollers 16 bit timer.  I need to clean up the clock before it goes into the micro.

From what I understand I can do one of two things.

1. Use a PLL to clean the clock signal.
2. Use a clock cleaner to reduce the phase noise.

Here is the kicker.  No matter what the solution is the most current the supply can use is 1.5mA.  I can't go into detail why this is the upper limit because this is for work but this is the absolute maximum.  I would appreciate any help.

[ejeffrey]

Do you know what phase noise you have and how much you can tolerate?  How about whether your are limited by close-in phase noise (essentially drift) or offset phase noise (like jitter).  Is it possible you can just replace the oscillator rather than try to clean it up, or is the clock coming from outside the system?  Also, how accurate does the absolute frequency need to be?

PLLs only work as well as the clocks you put into it.  So if you can't come up with a sufficiently low noise oscillator in your power budget a PLL won't help you.

[aep9690]

I can choose the clock that goes in the circuit, and I'm not sure how much jitter is in the circuit.  I plan on making a measurement tomorrow.

I suspected that if I used a PLL it wouldn't help because the clock is bad.  Knowing this I think I need to replace the oscillator.  I am using a standard 32MHz crystal oscillator now that is being divided to 256MHz.  The clocks jitter is causing my timers measurements to vary by +/- 100 counts or 390ns.  What kind of specification should I be looking for in a new clock to minimize jitter?

[Berni]

It might be the oscillator, but it might also be other things, like crosstalk from other high speed signals in to the clock trace, it could be a noisy power supply for the oscillator or the PLL, or it could even be wonky PLL settings. Fancy complex PLLs can be unstable in certain configurations.

Jitter can be easily visible on a digital scope by triggering on the clock and then turning the horizontal offset way out so you are looking about 1ms after your tigger point. For a proper crystal oscillator the waveform should not look fuzzy or wander left or right any. This method is sensitive enough to see the waveform drift when you heat up the crystal and see its tiny temp co.