Regarding connections in a CPLD schematic

[garvind25]

Hi,

I was planning to make a CPLD based hardware (for the first time ) and was going through the schematic of a Digilent board here:

https://reference.digilentinc.com/_media/coolrunner-ii:coolrunner-ii_sch.pdf

I have the following queries pls:

 The global output enable pins (2,3,5,6) are connected as general I/O pins in connector JI. So if I wanted to enable/disable all I/O pins of the IC, how could I do so? Just guessing but if I connect 3.3 v or GND to these pins, will it not enable/disable all I/Os (and the pins wont function as general I/Os)?
 
Global Set/Reset pin no. 143 is connected to VCC3v3/GND using an SPST (net label BTN0). But when the SPST is closed for GND connection, will it also not provide a direct path between VCC3v3 and GND (through a 4K7 resistor)? Is it not better to use a SPDT with a 10K resistor in series with central pin and VCC3v3 on one side and GND on other side of the SPDT? Also, what is this BTN1 (connected to pin no. 94)?
 
Clock divide reset (pin no. 35) is connected to port C of Atmel 90USB162 IC. Suppose I don’t want USB interface. Can I put a manual switch instead (for eg. a SPDT switch to connect the pin to either VCC/GND for enabling/ disabling the function)? If not, what are the work arounds?
 
Similarly, for what purpose is pin 124 (net label SW1) connected to an SPDT (to toggle between VCC3v3/GND—if so, the reason thereof)? Similarly why is pin 125 (net name MEM1) connected to 1 kB EEPROM (maybe for some kind of security purpose). If I don’t want to use it,  ie. I don’t want any security feature, I hope, the I/O pin is free for general usage. And finally where is pin 95 connected to (net name REG_RST)?
 
The unused I/O pins have been kept floating (the ones like pin no. 131, 132 etc). Is it the standard policy? Someone told me it contributes to power wastage in I/O blocks (internally). Is it true?
 
Finally, what are functional blocks and I/O banks. Where can I know about them and what things should I keep in mind while making the PCB for the CPLD.
 
 Looking forward to your kind help.
 
Thanking You,
Arvind Gupta.