Although I have never been stung by this in practice, I have known it happen to others. I remember when MAXII came out, 100 cycles was the norm. That is of course quite an old device, and most 'flash' based devices from that era and onwards have significantly higher endurance. With that said, the MaxV has 1000. This page is 6 years old (and has devices that are well over 15 years old) but mentions the subject:
http://dangerousprototypes.com/blog/2011/07/30/cpld-flash-memory-write-cycles/For most applications 100 is more than enough, and chances are the memory will be just as reliable after that number. But if you're learning, or using a dev board for education - where its going to get re-flashed very often - one can easily use that up in a week. Up to a thousand, and I think anyone would struggle to even approach that, again, unless its used in education and flashed tens of times a day.
Although I cannot lay my hands on the spec sheet from lattice I vaguely remember the NVCM MachXO3 has very few write cycles, as it is the low-cost version, but that isn't actually flash memory.
Notice I've only mentioned CPLD's here. I am unaware of an FPGA with flash (I'm sure they exist, just haven't used them) but then again the lines between CPLD and FPGA have been blurred in the past few years. I guess the MachX03 is an FPGA, but one with built-in config flash and low densities.