Rolling my own computers in the 90s

[joeqsmith]

I had posted a video some time ago about a small computer I had designed using a small FPGA back in the 90s.   This was not the first computer I had designed.   I pulled out one of my old PCs today take a few pictures of my last CPU prototyping board.   The board talks with the PC using a 16-bit ISA bus.   It has some static and dynamic RAM along with some FLASH.   The two larger FPGAs were programed from the ISA bus.   The FPGA in the PGA package performed the ISA bus interface, output the post codes, controlled a DDS the clocked the two larger FPGAs, as well as simulated the Altera programmer and security key.   

[DJLinux]

Good job I like it.
Currently a play with an very cheap ALTERA CycloneII EP2C5T144C8 board.

Where do you get this funky ISA prototype boards from ?

DJ

[legacy]

@joeqsmith
what was the purpose of your ISA board?

here I have an article, written in german, which talks about parallel computing over 68020 modules plugged into a PC on ISA16 bus

[jboard146]

 
Awesome!

[joeqsmith]

Good job I like it.
Currently a play with an very cheap ALTERA CycloneII EP2C5T144C8 board.

Where do you get this funky ISA prototype boards from ?

DJ

Back then, many places sold them.  I believe the larger 16-bit ISA board was made by Vector and I am guessing I bought it from Digi-Key.  Some I picked up from Jamaco and Newark.   

@joeqsmith
what was the purpose of your ISA board?

here I have an article, written in german, which talks about parallel computing over 68020 modules plugged into a PC on ISA16 bus

Really like most of my hobby projects, it was just for fun.  The board itself was designed to try some different ideas on how to design my own CPU. 

Awesome!

Thanks!  My plan was to put together a video showing how it all works.

[legacy]

my own CPU

is it RISC ? CISC ?
like R2K? like z80? 6800? 68000?

In my case, I am inspired by eight eight key, 88k
I am studying its User Manual

[joeqsmith]

my own CPU

is it RISC ? CISC ?
like R2K? like z80? 6800? 68000?

In my case, I am inspired by eight eight key, 88k
I am studying its User Manual

I assume you did not watch the video.   For the one in the video, I coded up the instruction set in a language I wrote that is similar to assembler.   These codes then define each op-code.   the instruction set is very similar to a Motorola 6801/11.  However I had added some of my own op-codes ti the mix.   I then wrote my own assembler for it.   It could run 6801 code directly except I did not try to follow the same number of clock cycles per instruction.   It runs much faster than the original part as well.     

The wire-wrap board shown in the pictures is really just a CPU prototyping setup.   It was not designed around any particular style of instruction sets.   

If you wanted to do this today, I would guess that the majority of evaluation boards would have much better hardware than what I had available back then.

[legacy]

I assume you did not watch the video.

yes, I am not able to play video with the machine I am currently logged-in
my 2011-mid bookAir has just died and I planning to buy a new one laptop (it won't be Apple)
so, currently I am using my old Unix Workstation, which comes with Netscape
it's a funny 90s browser, but it's not able to play videos

by the end of the next week I will get hands on my new laptop 

[legacy]

I then wrote my own assembler for it

here I have a similar problem: I have developed a new ISA(1), so I also need to develop a new assembler.
as you did, I have written myown assembler, too, and It works fine, but it does not support the linker,
instead, it builds the final binary directly

.asm ----> .{ bin, s19 }

supporting row binary(bin), and SREC(s19)

• out.data.{bin,s19} contain the data-section
• out.code.{bin,s19} contain the code-section

for this reason my assembler abuses of the #include directive, and everything (procedures, modules, etc) is an "include"

I have also developed a special tool that stuff the above row binaries into rom.vhdl
it's useful with you work with fpga


(1) similar to eight eight key, 88K, by Motorola

If you wanted to do this today

I have been working on my TAP (debug processor) for 3 years, just 3+3 hours a week during the week end

[joeqsmith]

Funny,  the video board in my old desktop died a couple of weeks ago.  Shorted out the power supply.   I need a new PC too, but need something with at least 1 PCI slot.

That's been many years ago but I think I just made a simple single pass assembler for the microcode.  It will take me a little time to figure out what all I was doing back then.   The PC is back together and will at least boot.   I had written some diagnostics for the board that load in a couple of test cores then exorcises the memory and buses.  I found the cables that go with it, so I plan to try testing the board in the next day or two.   These things never go smooth.   


TAP as in JTAG? Are you trying to make a computer that is geared toward JTAG specific control?    If so, do you have a blog where you are posting your progress?   I am interested!     I have written code by had for some of the Motorola parts using the BDM as well as JTAG.   What a nightmare.   If I were to do it today, it would be an FPGA with a FSM and Ethernet interface to the PC.     

Project for school, work or just for fun?

[legacy]

TAP as in JTAG? Are you trying to make a computer that is geared toward JTAG specific control?

yes and no

yes, T.A.P. stands for a Test Access Port, for monitoring the internal memories of the CPU, and this pushes you in the direction of IEEE 1149.1 JTAG
because JTAG is needed for detailed testing and instrumentation of the CPU, for instance to capture or replay pipeline stalls, hazards, and exceptions.

but no, JTAG only has access to I/O pins, so, to implement real emulators and trace tools you must have a logic block with special access to internal data and control paths and things become boring and complex (e.g. see the JTAG-ADI bridge made by the OpenRisc team), while in my case the TAP is just  the interface to the debug processor, which talks to the host over a serial protocol (different from SWD)

it works with CISC design, marvelously, It can be adapted to RISC (including pipeline, and superscalar pipeline, and multi core superscalar pipeline)
this part is underdevelopment, and it might be put in business, while the CISC design was born to "pass" a computer science examination in my university

If so, do you have a blog where you are posting your progress?

unfortunately no

I have written code by had for some of the Motorola parts using the BDM as well as JTAG.   What a nightmare.   If I were to do it today, it would be an FPGA with a FSM and Ethernet interface to the PC.     

MC68332? Here I have a BCCDI board, it comes with an hardware debug processor which talks over the serial line to the host. I have asked a friend to revers its protocol, and he has reported good news about that. We have a RiscPC, equipped with a PC-card, and a BDM cable attached to the LPT port. I can ask him to reverse  the BDM protocol (by a LA attached on the interface), as it's not well documented.

[obiwanjacobi]

That wiring alone is awesome!

[joeqsmith]

That wiring alone is awesome!

Thanks.  Glad those days are gone!   

I have written code by had for some of the Motorola parts using the BDM as well as JTAG.   What a nightmare.   If I were to do it today, it would be an FPGA with a FSM and Ethernet interface to the PC.     

MC68332? Here I have a BCCDI board, it comes with an hardware debug processor which talks over the serial line to the host. I have asked a friend to revers its protocol, and he has reported good news about that. We have a RiscPC, equipped with a PC-card, and a BDM cable attached to the LPT port. I can ask him to reverse  the BDM protocol (by a LA attached on the interface), as it's not well documented.

For BDM the 331, 332 and the 376.     For JTAG, the 306.    In both cases I wrote the code to bit bang the printer port.  Slow but very effective for bringing up the hardware for the first time.     

[legacy]

For BDM the 331, 332 and the 376.     For JTAG, the 306.    In both cases I wrote the code to bit bang the printer port.  Slow but very effective for bringing up the hardware for the first time.     

is there a public project? in our case (my friend and I) we will embed the BDM protocol into a cpld
so it will talk my TAP protocol, and it will connect to 332, in short it will be a BDM-TAP bridge

[joeqsmith]

It was for work some 20 years ago.   I did it for fun at home but used it for work.   Basically I was using the ports to test the hardware and identify any problems then program the boards.  The BDM was no problem but the the JTAG was pretty slow.   

Pictures showing my first prototype JTAG adapter.   

[joeqsmith]

Here is the first video of the set.   Enjoy.

[crispy_tofu]

Very cool. 

[joeqsmith]

Very cool. 

Thanks.  With any luck, the board will still run.   I powered up the PC and it looks like at least it still runs.

[bson]

Wooow!  Glad not to ever have to wirewrap again for prototyping... Cheap PCBs FTW!!!

[joeqsmith]

Wooow!  Glad not to ever have to wirewrap again for prototyping... Cheap PCBs FTW!!!

Agree.  I used to have a slit wrap spool gun when I was doing a lot of it.   These were all done by hand. 

Looks like the board is still functional.

[legacy]

Your work is impressive 

[joeqsmith]

The first version was done to pass a computer science examination (I got the result of 27/30 by my "computer architectures II, laboratory" professors , which is a decent vote, not brilliant), the second version attempts to be an hobby fun, the above is the simulator I wrote in order to reinvent the wheel, as I have designed a completely new ISA (it's RISC-like), which comes with its debug processor over its TAP, it stands for test access point, which is not jtag, and talks on the serial console with its own protocol.

No need to explain.  I have a copy of the IEEE 1149.1 standard, which was created by the JTAG subcommittee.   

[legacy]

No need to explain

so, I believe I'd better choose a more hipster name for the test access point of my debug processor inside the Arise processor, otherwise those guys in IEEE 1149.1 standard, which was created by the JTAG subcommittee, will ask me to pay the Copyright, and people will be not impressed (I apparently have already heard that name, uuuu  ) or confused (I have definitely already heard that name and it's already used to describe other things, my disappoint )

feel free to suggest me a funnier (1) one for Arise v3


(1) constrains: causing laughter or amusement, humorous, witty, comic, comical, droll, facetious, jocular, jockey, hilarious, hysterical, riotous, uproarious, entertaining, diverting, sparkling, scintillating, silly, farcical, slapstick, side-splitting, rib-tickling, laugh-a-minute, wacky, zany, off the wall, a scream, rich, priceless, difficult to explain and understand, strange

(kidding )

[joeqsmith]

No need to explain

so, I believe I'd better choose a more hipster name for the test access point of my debug processor inside the Arise processor, otherwise those guys in IEEE 1149.1 standard, which was created by the JTAG subcommittee, will ask me to pay the Copyright, and people will be not impressed (I apparently have already heard that name, uuuu  ) or confused (I have definitely already heard that name and it's already used to describe other things, my disappoint )

feel free to suggest me a funnier (1) one for Arise v3


(1) constrains: causing laughter or amusement, humorous, witty, comic, comical, droll, facetious, jocular, jockey, hilarious, hysterical, riotous, uproarious, entertaining, diverting, sparkling, scintillating, silly, farcical, slapstick, side-splitting, rib-tickling, laugh-a-minute, wacky, zany, off the wall, a scream, rich, priceless, difficult to explain and understand, strange

(kidding )

I never picked up that that you were calling TAP had nothing to do with the industry standard TAP until now.   

For BDM the 331, 332 and the 376.     For JTAG, the 306.    In both cases I wrote the code to bit bang the printer port.  Slow but very effective for bringing up the hardware for the first time.     

is there a public project? in our case (my friend and I) we will embed the BDM protocol into a cpld
so it will talk my TAP protocol, and it will connect to 332, in short it will be a BDM-TAP bridge

I'm assuming  when you write BDM you actually mean Motorola's BDM standard.   Do they even sell the 332 anymore?   What is what you call TAP doing that I can't achieve with the BDM?   I tested a lot of hardware with that BDM port using nothing more than a GAL, a printer port and some C code.   I still have an old HP BDM interface along with the P&E.     

[legacy]

I never picked up that that you were calling TAP had nothing to do with the industry standard TAP until now

witten in this topic, just a few posts above

yes, T.A.P. stands for a Test Access Port, for monitoring the internal memories of the CPU, and this pushes you in the direction of IEEE 1149.1 JTAG
because JTAG is needed for detailed testing and instrumentation of the CPU, for instance to capture or replay pipeline stalls, hazards, and exceptions.

but no, JTAG only has access to I/O pins, so, to implement real emulators and trace tools you must have a logic block with special access to internal data and control paths and things become boring and complex (e.g. see the JTAG-ADI bridge made by the OpenRisc team), while in my case the TAP is just  the interface to the debug processor, which talks to the host over a serial protocol (different from SWD)

I'm assuming  when you write BDM you actually mean Motorola's BDM standard.

if I do not tell you what an acronym is referring to, you can assume it's within the common standard, and in this case, BDM is Motorola BDM

What is what you call TAP doing that I can't achieve with the BDM?

my TAP is currently used in my Arise Softcore, which I have implemented in fpga. A software simulator (see the above post) is also existing as proof of concept.

Concerning my 332 board, I am going to build a bridge between my TAP and BDM, in this case the interface to MC68332 will be BDM, while the interface to my host PC, and all the software I have written to handle it, will be TAP

my Eprom emulator is also able to talk my TAP, as my TAP comes with a flexible protocol