Route the 3.3v supply to an LQFP microcontroller in a 2-layer PCB

[luiHS]

Hi.

I have seen (picture attached) this manual routing of +3.3v supply to a LQFP microcontroller, in a 2 layer PCB, I found it interesting. I always route the decoupling capacitors by hand, from the pins of the microcontroller to the capacitor, but I did not manually route the supply of the + 3.3v. All my designs work, but I think it's better to change the routing of the + 3v3 as in the attached image.

When I make a 4-layer PCB, there's no problem, the 2 internal layers are GND and + 3v3, and then when I put decoupling capacitors, I add two vias near the capacitor, one to GND and another to + 3v3, which connect directly to the internal supply layers.

The question is what is the ideal way to route in a 2-layer PCB, the supply of 3.3v to a microcontroller.
Suggestions?.

Its ok what you see in the attached image? They hand-route a track to the center of the microcontroller in the bottom layer, add a kind of polygon (which is not such, but a track that closes on itself creating a rectangle), and add vias in the Top layer with tracks to each +3.3v pin of the microcontroller.

Greetings.

[nctnico]

I don't like it because it cuts the ground plane too much. On a 2 layer board I always put a supply (3.3V) copper pour on the top layer and keep the ground plane solid under the microcontroller. Any unbalance in the power supply connections will cause unwanted currents to flow through the chip instead of through the circuit board. I also make sure the decoupling capacitors have a direct path to the ground of the microcontroller. This method does limit the routing of trace because the area under the microcontroller can't be used but with some extra space around the microcontroller to route signals around the microcontroller this shouldn't be a big problem.

[T3sl4co1l]

This isn't very good; it's actually really good if you place several ceramic chip bypass caps around the perimeter of that polygon, if you don't mind bottom side component placement.

Best scheme: lay out the circuit as a single placement and routing layer, as much as possible.  Leave the other layer as solid ground, as much as possible.

Where traces need to cross, drop to the opposite layer for only a short length (this may entail more vias than a direct route, that's fine, vias are free).

Note that traces, vias, rows of component pads and so on, cause obstructions on one or both layers, so traces MUST be routed around them (or through, if connected).  Wide pitch components sometimes allow routing through (mainly SOIC and DIP), but if the traces aren't connecting on the other row, you'll probably find it causes more congestion than it's worth.

QFNs are the most annoying, where you might not have any escape route from underneath the chip, so you have to drop vias there, or spend more space around it getting traces to the sides they need to be on.  QFPs (no thermal pad) have some space there, but you should prefer ground there on one layer or the other.  Or a well-bypassed supply, or both.

Finally, group traces together into buses of sorts, and fill in the negative space around them with ground pour.  Stitch this with vias, at least at every peninsula.  Don't bother to fill small islands; medium islands, connect with vias, just one is fine for smaller ones, use two or more for larger islands.

In this way, even where many traces have to be routed on the opposite layer, ground is never far away, whether above, below or beside.  Note that anywhere two buses of traces cross, there is a complete hole in both top and bottom ground.  Keep these holes small and infrequent.

In general, commit about half the layers to supply nets, in priority order.  The remaining supplies are then routed as any other signal, with suitable considerations for trace width and bypassing.

For the two-layer case, some routing on the "plane" layer is inevitable, and that's why you want to keep opposite-layer routes small.  That's also why you want to fill ground on both sides, so it averages out to, hopefully a bit more than one poured layer actually.

When you have four layers, for example, you can afford two for supplies and the rest for routing.  GND takes priority, then whatever VCC supply/ies can be the other.  Doesn't have to be a solid layer, likely you'll have different zones depending on what supply takes priority in a given area.  (You can also fill the routing layers with ground or whatever, but it's harder to stitch -- you have to check four layers for via placement -- and doesn't have nearly as much benefit, as the inner layers do a surprisingly good job of shielding despite not being actually on top.)

Tim

[bson]

I'd use a 4 layer board...  The simple reason being both to ensure quality power planes, but also to have two full, mostly unrestricted layers for signal routing.  Even if the routing is simple point to point, just the sheer trace volume will make the PCB size inflate considerably with only two layers.  And then, invariably, blocks of those signals will need to cross blocks of other signals, unless you have some extremely lucky pinouts.  But LQFP-144... (or even 100, as in your example) - if I don't need 144 pins I use a variant in a smaller package, although sometimes unused pins provide useful signal spacing, and if I do need them the sheer volume means I start with a 4 layer board and possibly might consider a 6 layer one if things go south.  But 4 to 6 also strongly suggests blind, maybe buried, vias or just the via density itself sets a lower size limit (full vias need to go through the power planes so will cut them up, and will need to be routed around in the other additional signal planes).

[David Hess]

If the supply connections are decoupled to the ground plane properly, then it does not matter how the supply connections arrive.

This isn't very good; it's actually really good if you place several ceramic chip bypass caps around the perimeter of that polygon, if you don't mind bottom side component placement.

I have never had a problem doing it that way on a layout like luiHS showed.  With the decoupling capacitors, the power plane under the IC becomes an AC coupled extension of the ground plane.  It is not as good as a continuous ground plane but it works well enough.  You might even be able to do it with the decoupling capacitors on the top surrounding the IC if space is available for them.

[nctnico]

If the supply connections are decoupled to the ground plane properly, then it does not matter how the supply connections arrive.

This isn't very good; it's actually really good if you place several ceramic chip bypass caps around the perimeter of that polygon, if you don't mind bottom side component placement.

I have never had a problem doing it that way on a layout like luiHS showed.  With the decoupling capacitors, the power plane under the IC becomes an AC coupled extension of the ground plane.  It is not as good as a continuous ground plane but it works well enough.  You might even be able to do it with the decoupling capacitors on the top surrounding the IC if space is available for them.

If you look closely at the picture you'll see there is no continuous power plane under the chip! The square in the middle is 3V3. IMHO what the OP has shown in the picture is about the worst way to implement the power supply.

[T3sl4co1l]

If you look closely at the picture you'll see there is no continuous power plane under the chip! The square in the middle is 3V3. IMHO what the OP has shown in the picture is about the worst way to implement the power supply.

We're saying if bypass caps were added around that shape.

The equivalent plane would then be two fills connected with spokes, not ideal but certainly better than pictured.  And yeah, I mentioned in the very first place, it's not very good as shown.

Tim