SD 3.0 host controller core implementation (UHS-i mode)

[Saad]

Hello,

I wish to develop a SD 3.0 host controller core in UHS-i mode using just the simplified spec delivered by SD Association (I don't know whether there is another better free resource), and :

1-till now, I still can't confirm if just that simplified spec is enough to get this core up, i hope not to go through a dead end road..

2- the reason beside attempting to develop this core from the bottom point is the high license cost of SD controller, thus will i need to cover those huge fees even if i take this approach (develop my own core using simplified spec for just research purpose). But if i do need to, there is some practical way to get ride of it? (i will appreciate if you can also share with me the references if possible).

3- Knowing that i'm not very familiarised with FPGA design, how much time it would take to complete this work?

I will appreciate any help,
thanks,

Saad.

[Someone]

3- Knowing that i'm not very familiarised with FPGA design, how much time it would take to complete this work?

First you'll need to be come an expert in FPGA design, then it might only take a few months. This is very difficult to get right with a combination of complex state machines, varying vendor implementations, and all the hardware challenges of high speed physical links.

[marshallh]

You can get 23mbyte/second without UHS mode.

If you want to implement UHS, you must also add all the lower functionality (25mhz, 50mhz, 4bit, etc).

If you are an FPGA noob it will take several months of very hard work and learning.