SDRAM vs OctoSPI

[luiHS]

 
Hello.

What is faster SDRAM or OctoSPI?

I need to develop a board with RT1020 LQFP144, the idea is to boot from QSPI or SD, and run from SDRAM. The compilation process allows configuring the Link to RAM parameter in the Linker Script, so that the software boot from SD or QSPI, which it copies and run automatically from SDRAM.

I need a fast storage, to run the software and store large data tables (from 16 to 20Mbit), so I thought about using SDRAM, but I have read that the OctoSPI memories are actually faster because the bus is 64 bits, while that the SDRAM bus is 32 bits, plus they need less pins from the microcontroller.

There is a third option, hyperflash, but I think this is not as fast as SDRAM.

[ShowKemp]

What is faster SDRAM or OctoSPI?

... but I have read that the OctoSPI memories are actually faster because the bus is 64 bits, while that the SDRAM bus is 32 bits, plus they need less pins from the microcontroller.

According to your own post, OctoSPI are faster.

[asmi]

I need a fast storage, to run the software and store large data tables (from 16 to 20Mbit), so I thought about using SDRAM, but I have read that the OctoSPI memories are actually faster because the bus is 64 bits, while that the SDRAM bus is 32 bits, plus they need less pins from the microcontroller.

Where did you read that? As far as I can tell OctoSPI is just another name for a version of HyperBus, which means it has 8bit-wide DDR data channel, which can run up to 200 MHz DDR (so 400 MT/s). This is the same bus used in "HyperFlash".

[luiHS]

Where did you read that? As far as I can tell OctoSPI is just another name for a version of HyperBus, which means it has 8bit-wide DDR data channel, which can run up to 200 MHz DDR (so 400 MT/s). This is the same bus used in "HyperFlash".

From this NXP document:
https://community.nxp.com/servlet/JiveServlet/download/340655-1-426559/boot_to_sdram.zip

" NOTE: While RT does support booting to SDRAM using these steps, we recommend using XIP from serial NOR on the FlexSPI interface when possible. The FlexSPI controller is connected to a 64-bit internal bus, but the SEMC which is the SDRAM controller on RT uses a 32-bit bus. So XIP from FlexSPI will usually provide better performance than booting code to SDRAM. "

[PCB.Wiz]

Where did you read that? As far as I can tell OctoSPI is just another name for a version of HyperBus, which means it has 8bit-wide DDR data channel, which can run up to 200 MHz DDR (so 400 MT/s). This is the same bus used in "HyperFlash".

From this NXP document:
https://community.nxp.com/servlet/JiveServlet/download/340655-1-426559/boot_to_sdram.zip

" NOTE: While RT does support booting to SDRAM using these steps, we recommend using XIP from serial NOR on the FlexSPI interface when possible. The FlexSPI controller is connected to a 64-bit internal bus, but the SEMC which is the SDRAM controller on RT uses a 32-bit bus. So XIP from FlexSPI will usually provide better performance than booting code to SDRAM. "

That seems to be talking about buses inside the NXP part, not the devices.
That also has your answer, if you are looking for XIP speed.
NXP should indicate what memories it can boot from, and OctaSPI is not quite a clone of HyperBUS, so comes down to what their silicon supports.

[technix]

This design sounded a bit weird to me: why would NXP make SDRAM run slower than QSPI? Isn't DDR SDRAM often capable of running much faster than any form of QSPI/OctaSPI? Also I think that per-byte cost of Flash is more expensive than SDRAM, so for larger projects it can even make sense to use a large SDRAM rnning memory and heavily compress the on-Flash program code?

[luiHS]

This design sounded a bit weird to me: why would NXP make SDRAM run slower than QSPI? Isn't DDR SDRAM often capable of running much faster than any form of QSPI/OctaSPI? Also I think that per-byte cost of Flash is more expensive than SDRAM, so for larger projects it can even make sense to use a large SDRAM rnning memory and heavily compress the on-Flash program code?

Any RAM will always be faster than any flash. But NXP says that in RT microcontrollers, SDRAM is connected to 32-bit data bus, meanwhile OctoSPI Flash is interally connected to 64-bit data, but then they say there is better performance with OctoSPI than with SDRAM.

At any rate, my idea is boot from QSPI and compile to run from RAM, this do that microcontroller automatically boot from QSPI, copy program to SDRAM and run from SDRAM. External 256Mbit and 512Mbit SDRAM are really cheap, so good option.

[NorthGuy]

Any RAM will always be faster than any flash.

If you have a device which can fetch data from memory at speed X, then two parallel devices will be able to fetch data at speed 2*X. Therefore, by paralleling (that is increasing bus size) you can make a device which works at any reasonable throughput (regardless of whether it is flash or RAM). But it is only true if you want to transfer large consecutive blocks (e.g. copy ROM to RAM).

However, when you want to run CPU from some sort of memory, the throughput may not be that important, because of higher latencies. When the CPU execution jumps to a new place, the memory needs time to fetch the data for the new address and transmit it to the CPU. No matter how wide is your bus, it doesn't improve latencies a bit. Flash will have longer latencies anyway.

Now, you decide what you want. If you want to move large blocks of memory then go with high throughput. If, on the other hand, you want to react to something very fast, go with low latencies.

Of course, it all goes through internal caches, so it is often hard to predict what you get.

[technix]

At any rate, my idea is boot from QSPI and compile to run from RAM, this do that microcontroller automatically boot from QSPI, copy program to SDRAM and run from SDRAM. External 256Mbit and 512Mbit SDRAM are really cheap, so good option.

You can even compress the main image - squeeze a 25MB image into a 16MB Flash chip maybe, and use an decompression bootloader.