Author Topic: Signal integrity analysis of PCBs  (Read 1001 times)

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Offline garvind25

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Signal integrity analysis of PCBs
« on: November 25, 2017, 02:42:38 AM »
Hi,

I am new to signal integrity concept and wanted to know about signal integrity analyses for a 25 MHz range FPGA based PCB. What all are to be checked for SI analyses and how can it be done. I know the usage of CST microwave. Will that be helpful pls.? It will be nice if anyone can list the analyses/ checks to be made for SI in PCBs as a starting point of my search.

Thanks,
Arvind Gupta
 

Online dmills

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Re: Signal integrity analysis of PCBs
« Reply #1 on: November 26, 2017, 04:37:05 AM »
For something as slow as 25MHz, my basic questions would be 'is everything run over a solid continuous reference plane' and 'have you controlled the edge rates'? 

Get those right, get the power decoupling reasonable and your basically covered for SI given you are doing wiggly DC sort of rates.

Regards, Dan.
 

Offline garvind25

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Re: Signal integrity analysis of PCBs
« Reply #2 on: December 21, 2017, 02:25:47 AM »
Thanks for your reply. What do you mean by edge rate pls? Also when you say solid continuous reference plane, do you mean a continuous gnd plane ?

Regards,
Arvind Gupta
 

Offline suicidaleggroll

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Re: Signal integrity analysis of PCBs
« Reply #3 on: December 21, 2017, 03:00:45 AM »
Edge rate control is done with either drive-strength limiting in the source or series resistors close to the source.  For example, sticking 100R resistors on all of your serial clock and data lines close to the source (eg: clock, CS, MOSI for a SPI master, MISO for a spi slave) is usually a decent start.

Yes he means a solid ground plane, so the return current for any of your relatively high speed lines is free to travel on the ground plane directly beneath the trace, rather than having to detour around because of an obstruction, increasing the inductance and EMI.


Remember that current flows in a loop.  If device A drives a line high, the current will flow out of device A, into device B where it's attached, through device B's internal circuitry, out device B's ground pin, through the PCB ground plane, back to device A's ground pin.  For very low frequencies, the term "current follows the path of least resistance" is true.  This ground return current will bias toward whatever path gives it the least resistance, usually a straight shot between the two devices.  As the frequency increases, this starts to break down.  The truth is that the current doesn't follow the path of least resistance, it follows the path of least impedance.  For DC, impedance is just resistance, but when the frequency increases, reactance starts to play a part as well.  When you get into double digit MHz, the impedance will be heavily affected by reactance, which means the return current won't just follow a straight shot from device B back to device A anymore, it will follow whatever path minimizes reactance.  Any loop created by the source current  and return current paths is an inductor.  To minimize loop area and inductance, the return current will tend to follow a path directly underneath the trace.  It's important you allow this to happen by having a solid, obstruction-free ground plane.  Don't run any other traces on this ground plane if you can help it, and certainly don't run any traces directly under your high speed lines or you'll obstruct the return current for those lines.
« Last Edit: December 21, 2017, 03:13:12 AM by suicidaleggroll »
 
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Online ejeffrey

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Re: Signal integrity analysis of PCBs
« Reply #4 on: December 23, 2017, 03:52:31 PM »
Not that for AC signal analysis, GND and power planes are mostly equivalent.  They are tied together by the bypass capacitor close to each chip.  So as long as your bypassing is OK you can have signals whose return path is an unbroken GND plane or an unbroken power plane.  The important thing is that the return path be unbroken.

When you go through a via that you are changing the reference plane.  Consider a typical 4 layer stackup: signal / gnd / power / signal.  When your signal transitions from top to bottom plane using a via, the return current jumps from gnd to power.  You should place a bypass capacitor near the via to allow the return current to make the jump.
 

Offline garvind25

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Re: Signal integrity analysis of PCBs
« Reply #5 on: December 23, 2017, 10:16:18 PM »

 To minimize loop area and inductance, the return current will tend to follow a path directly underneath the trace.  It's important you allow this to happen by having a solid, obstruction-free ground plane.  Don't run any other traces on this ground plane if you can help it, and certainly don't run any traces directly under your high speed lines or you'll obstruct the return current for those lines.

Thanks for the detailed reply. Could you pls. explain what is meant by 'path directly under the trace' means. Are you suggesting that the high speed signal passes through the top surface of a trace and return signal through bottom surface of the same trace?  Or are you suggesting that for multi layer pcb if a trace has a high frequency signal, it should not have any other trace directly beneath it  Or I did not get it properly :-\.

For two layer PCB, the gnd plane and signal tracks share the same plane, there would be gaps in the ground plane(s) to accommodate for the signal tracks{even if both to and bottom gnd planes are connected by multiple vias}. So will such pcbs have higher reactance by default.

Also, at what frequency should I start bothering about signal integrity pls?

Thanks and Regards,
Arvind Gupta
 

Offline ThomasDK

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Re: Signal integrity analysis of PCBs
« Reply #6 on: December 25, 2017, 02:57:15 AM »
Thanks for the detailed reply. Could you pls. explain what is meant by 'path directly under the trace' means. Are you suggesting that the high speed signal passes through the top surface of a trace and return signal through bottom surface of the same trace?
No, only the signal passes through the trace. The return current goes through the ground plane, but follows the path of the signal trace back to the source.

Quote
Or are you suggesting that for multi layer pcb if a trace has a high frequency signal, it should not have any other trace directly beneath it  Or I did not get it properly :-\.
Exactly, a trace beneath a signal trace will break the ground plane and disturb the return current flowing below the signal trace.

Quote
For two layer PCB, the gnd plane and signal tracks share the same plane, there would be gaps in the ground plane(s) to accommodate for the signal tracks{even if both to and bottom gnd planes are connected by multiple vias}. So will such pcbs have higher reactance by default.

Also, at what frequency should I start bothering about signal integrity pls?

For sinusoidal (analog) signals everything below 100 MHz will probably be fine without huge signal integrity concerns.

For square waves (digital signals), it's more a matter of the rise and fall times of the signal than the actual frequency.

A 10 MHz digital signal can have frequency components of hundreds of MHz, depending on the rise time.

Thomas

 


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