Hello,
The following XC8 C code for PIC18F26K20 Builds successfully but doesn’t work.
Please help make it work?
All it is supposed to do is output on RC2 what it reads as an input on RB0. (They are both Digital I/O ports)
I cannot see why it wont work.
The following is the crux of the entire code………..
while(1) {
if (PORTBbits.RB0 == 0) {PORTCbits.RC2 = 0;}
__delay_ms(1);
if (PORTBbits.RB0 == 1) {PORTCbits.RC2 = 1;}
__delay_ms(1);
}
…..surely there is nothing wrong with this?
Here is the complete code listing……
/*
* File: main.c
*/
//This file is very simple code.
//It simply puts out on RC2 what it reads on RB0. (HIGH or LOW)
/*
Generated Main Source File
File Name:
main.c
Description:
* Generation Information :
Device : PIC18F26K20
The generated drivers are tested against the following:
Compiler : XC8 v1.38
MPLAB : MPLAB X IDE v3.61
*/
#include <xc.h>
#include <stdint.h>
#include <stdlib.h>
#define _XTAL_FREQ 16000000
// CONFIG1H
#pragma config FOSC = INTIO67 // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7)
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
// CONFIG2L
#pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOREN = OFF // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
#pragma config BORV = 18 // Brown Out Reset Voltage bits (VBOR set to 1.8 V nominal)
// CONFIG2H
#pragma config WDTEN = OFF // Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register)
#pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)
// CONFIG3H
#pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = OFF // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
#pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
#pragma config HFOFST = OFF // HFINTOSC Fast Start-up (The system clock is held off until the HFINTOSC is stable.)
#pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
// CONFIG4L
#pragma config STVREN = OFF // Stack Full/Underflow Reset Enable bit (Stack full/underflow will not cause Reset)
#pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
#pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
// CONFIG5L
#pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-003FFFh) not code-protected)
#pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (004000-007FFFh) not code-protected)
#pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (008000-00BFFFh) not code-protected)
#pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (00C000-00FFFFh) not code-protected)
// CONFIG5H
#pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
#pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
// CONFIG6L
#pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-003FFFh) not write-protected)
#pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (004000-007FFFh) not write-protected)
#pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (008000-00BFFFh) not write-protected)
#pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (00C000h-00FFFFh) not write-protected)
// CONFIG6H
#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
// CONFIG7L
#pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)
// CONFIG7H
#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
void main(void)
{
OSCCON = 0x72; // 16MHz
OSCTUNE = 0x00;
//Set up Special Function Registers
ANSEL = 0x00; //Enable all input buffers (not using analog functions)
ANSELH = 0x00; //Enable all input buffers (not using analog functions)
ADCON0 = 0x00; //ADC disabled
CM2CON0 = 0x00; //Comparator 2 disabled
CM1CON0 = 0x00; //Comparator 1 disabled
CCP2CON = 0x00; //Disable PWM and capture compare modules.
CVRCON = 0x00; //Disable internal voltage reference (of comparator))
TRISA = 0b00000110; //AJM checked
TRISB = 0b00001111; //AJM checked //RB0 is input.
TRISC = 0b00000000; //AJM checked. //RC2 = Output.
INTCON = 0x00; //Disable all interrupts
INTCON2 = 0x80; //Disable PORTB pullups
SLRCON = 0x00; //All PORTB outputs slow at standard rate.
PORTCbits.RC2 = 0; //LEDs OFF
while(1) {
if (PORTBbits.RB0 == 0) {PORTCbits.RC2 = 0;}
__delay_ms(1);
if (PORTBbits.RB0 == 1) {PORTCbits.RC2 = 1;}
__delay_ms(1);
}
return;
}
Home
Help
Search
Login
Register
