I'm trying to figure out a good way to describe a parameterized bus multiplexer.
The idea is to describe something like this
wire [7:0] in [0:3];
wire [7:0] out = ({8{sel[0]}} & in[0]) | ({8{sel[1]}} & in[1]) | ({8{sel[2]}} & in[2]) | ({8{sel[3]}} & in[3]);
but for a variable number of inputs.
I've got something like this:
genvar i;
wire [7:0] part [N-1:0];
generate for (i = 0; i < N; i = i + 1) begin: data_mux
if (0 == i)
assign part[i] = {8{sel[i]}} & in[i];
else
assign part[i] = part[i-1] | {8{sel[i]}} & in[i];
end
endgenerate
assign out = part[N - 1];
This works, but does not look great.
Any ideas how to simplify this?
The final goal it to get a mux with one-hot select input, and 0 on the output if noting is selected. I need to stay with Verilog-2001, no SystemVerilog here.