Author Topic: Single-stepping a clock on Spartan 3 & 6  (Read 2654 times)

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Offline hamster_nzTopic starter

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Single-stepping a clock on Spartan 3 & 6
« on: December 23, 2015, 02:15:55 am »
I had a spare hour last night, and played around with allowing an FPGA design to run at full speed, or to be switched to a 'single step' mode (with a push button to advance the clock by one tick).

My little "proof of concept" design is http://hamsterworks.co.nz/mediawiki/index.php/Single_Step

Somebody might find it helpful, esp if somebody has a blinkenlights front panel to their home-brew CPU.

It is also a good way to discover what is so special about the BUFGMUX primitive.... it has a pretty subtle-but-essential difference in behavior from a two-input MUX, which is also a P.I.T.A in some use-cases.
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Offline Bruce Abbott

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Re: Single-stepping a clock on Spartan 3 & 6
« Reply #1 on: December 23, 2015, 05:12:57 pm »
It is also a good way to discover what is so special about the BUFGMUX primitive.... it has a pretty subtle-but-essential difference in behavior from a two-input MUX,
I am trying to learn VHDL but most of the tutorials I have found suck (they just throw code at you and don't explain what all the symbols mean). Hoping you can answer a few newbie questions about your code:-

1. bufgmux is a 'primitive', which is a core logic component like an AND gate or a flip-flip, right? Is this one specific to the Spartan 3E or is there an equivalent in most other FPGAs?

2. In what way is bufgmux different from a normal 2-input MUX?

3. Why is a normal 2-input MUX a P.I.T.A in some cases?

4.  The diagram shows 2 logic blocks called 'madd_counter[7]...' and 'fd' which don't appear in your code? Why does 'fd' not have an instance name?

5. You say that the 'trick' is in buffering the clock correctly before sending it into the BUFGMUX. Why do you need to do this, and what exactly does the buffer do?
 
   
 

Online langwadt

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Re: Single-stepping a clock on Spartan 3 & 6
« Reply #2 on: December 23, 2015, 05:57:05 pm »
It is also a good way to discover what is so special about the BUFGMUX primitive.... it has a pretty subtle-but-essential difference in behavior from a two-input MUX,
I am trying to learn VHDL but most of the tutorials I have found suck (they just throw code at you and don't explain what all the symbols mean). Hoping you can answer a few newbie questions about your code:-

1. bufgmux is a 'primitive', which is a core logic component like an AND gate or a flip-flip, right? Is this one specific to the Spartan 3E or is there an equivalent in most other FPGAs?

2. In what way is bufgmux different from a normal 2-input MUX?

3. Why is a normal 2-input MUX a P.I.T.A in some cases?

4.  The diagram shows 2 logic blocks called 'madd_counter[7]...' and 'fd' which don't appear in your code? Why does 'fd' not have an instance name?

5. You say that the 'trick' is in buffering the clock correctly before sending it into the BUFGMUX. Why do you need to do this, and what exactly does the buffer do?
 
   

primitives are specific to a certain FPGA but most current FPGAs have similar primitives

bufgmux is special for clocks, the G means global, it can connect the special wires used to distribute clocks on the chip

bufgmux is specially made to switch between clocks without making glitches or short clock periods

clocks are distributed via dedicated clock wires on the chip, you need the right combination of buffers etc. to connect to those wires
if you don't use any of the special primitives it is normally done automatically by the tools

 

Offline exmadscientist

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Re: Single-stepping a clock on Spartan 3 & 6
« Reply #3 on: December 23, 2015, 06:52:13 pm »
It is also a good way to discover what is so special about the BUFGMUX primitive.... it has a pretty subtle-but-essential difference in behavior from a two-input MUX,
I am trying to learn VHDL but most of the tutorials I have found suck (they just throw code at you and don't explain what all the symbols mean). Hoping you can answer a few newbie questions about your code:-

1. bufgmux is a 'primitive', which is a core logic component like an AND gate or a flip-flip, right? Is this one specific to the Spartan 3E or is there an equivalent in most other FPGAs?

2. In what way is bufgmux different from a normal 2-input MUX?

3. Why is a normal 2-input MUX a P.I.T.A in some cases?
BUFGMUX is a dedicated hardware circuit on the FPGA used exclusively for clock buffering and multiplexing. As langwadt said, it is special because it connects to the clock wiring (aka clock routing) wires on the chip as an input. Very few things inside the FPGA can drive the clock wires. All FPGAs have some way to do this, but BUFGMUX is specific to Xilinx FPGAs. (And maybe even specific to the Spartans? I don't know, the Spartan-6 is the only FPGA I've worked with professionally.) It is described in much more detail in Xilinx UG382, Spartan-6 Clocking Resources (pdf).

Quote
4.  The diagram shows 2 logic blocks called 'madd_counter[7]...' and 'fd' which don't appear in your code? Why does 'fd' not have an instance name?
madd_counter... is the hardware synthesis of the clocked counter <= counter + 1 operation. fd is just a D flip-flop that buffers the (combinatorial) output of the add circuitry and synchronizes it to the clock. It is unnamed because it's really just glue that binds the synchronous logic together. If there was some downstream logic using this output, fd might get absorbed directly into that logic, depending on exactly what its inputs require.

Quote
5. You say that the 'trick' is in buffering the clock correctly before sending it into the BUFGMUX. Why do you need to do this, and what exactly does the buffer do?
Unless I'm mistaken and there's more going on here than meets my eye, the trick is just the use of the BUFG to buffer the clock signal before routing it to the BUFGMUX. This is necessary because BUFGMUX's inputs only connect to the clock wiring. BUFG is how you put a signal onto the clock routing.
 

Offline hamster_nzTopic starter

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Re: Single-stepping a clock on Spartan 3 & 6
« Reply #4 on: December 23, 2015, 07:55:11 pm »

2. In what way is bufgmux different from a normal 2-input MUX?

3. Why is a normal 2-input MUX a P.I.T.A in some cases?


Others have done a pretty good job of the other answers, but these two need a bit more explanation.

As others pointed out, a BUFGMUX is used to switch clock signals as they  head onto the 'low skew' clock networks. These clock networks are specially set up so that the signal can reach all areas of the chip at exactly the same time (not by magic, but by ensuring that the delays along the way are equal).

A BUFGMUX differs from a normal MUX in that when you request that it switches between signals it waits until it has seen a falling edge on the currently selected input clock, and then while holding the output clock high it waits until the new input clock is high before it completes the switch over.

ASCIIart logic diagram....
Code: [Select]
SEL:   _______________________XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
CLK0: __XXXXX____XXXXX____XXXXX____XXXXX____XXXXX____XXXXX_
CLK1: XXXXXXXXXXXX______________XXXXXXXXXXXX______________XX
OUT:  __XXXXX____XXXXX____XXXXXXXXXXXXXXXXXX______________XX

A simple 2-input MUX would give you
Code: [Select]
OUT:  __XXXXX____XXXXX____XXXXX_XXXXXXXXXXXX______________XX

This process ensures that during the transition there is no pulse with a width shorter than that of puise width in either input clock.  If these short 'runt' pulses were to occur the synchronous nature of the logic running on off of the OUT clock would be broken.

However, that also shows you the problem with the scheme - you can't switch off of a clock that isn't ticking, and usually one from an external source. One solution I've used for this problem is that I add an XOR into the path of the unreliable clock, (e.g. PIN -> XOR -> BUFGMUX), and then if the design detects that the clock isn't ticking it can ask the BUFGMUX to switch, then waggle the input to the XOR gate to inject a couple of transitions, forcing the switch to occur. Very ugly, but it worked.

In this design, you can switch the high speed clock back off and on with the clock select switch, but if you use the single step button the design it won't start running again when you switch back. It is stuck on the 'stopped' clock. You have to push the button again to give edges to the BUFGMUX, allowing it to finish the switch.

It is a subtle but still interesting behavior.

« Last Edit: December 23, 2015, 07:57:37 pm by hamster_nz »
Gaze not into the abyss, lest you become recognized as an abyss domain expert, and they expect you keep gazing into the damn thing.
 


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