Small Form factor FPGA/CPLD chip

[mikeselectricstuff]

Decoding is trickier than encoding as you need to.either phaselock to the manchester clockrate or oversample. Capture peripherals can be very useful though, 564k is probably doable on a pic8 at 32MHz

[NorthGuy]

Decoding is trickier than encoding as you need to.either phaselock to the manchester clockrate or oversample. Capture peripherals can be very useful though, 564k is probably doable on a pic8 at 32MHz

I think if you don't use logic cells and do it in traditional MCU way using Input Capture (called CPP on PIC16/18), you still can do it on PIC16.

If you only sample rising edges, you can reconstruct the data (provided you had some locking sequence before the packed) - the distance between edges will be 1 clock or 1.5 clocks - that's all you need to know. Thus you have roughly 2 us to enter the interrupt, process data, and leave the interrupt. All you need to figure out if the distance between pulses was 1 or 1.5 clocks. Comparing to 1.25 will do the trick. Then you append your data accordingly and transmit it out (say by sending through SPIBUF).

1 clock is roughly 2 us, 16 cycles on PIC16F1*, less 4 cycles for interrupt entry/exit. 12 cycles should be enough to subtract two numbers and compare the difference to 10 (1.25 cycles) and then record the data bits and write SPIBUF if needed.

On PIC16F1454 you would have 20 cycles, and that is plenty to decode everything and store the byte in the USB buffer, leaving few cycles to spare for the USB engine to send data to PC.

On PIC18, you get 28 cycles, but you may need to do some context saving/restoring. It is actually more than you need. So, you can get another CPP running and detect falling edges. This will let you do auto-locking and error detection.

[PCB.Wiz]

Hi everyone
I am working on a manchester decoding, I have the code running on a zybo board FPGA.  I want to design a small standalone digital board stand that can run my VHDL. Can anyone recommend a small form factor FPGA/CPLD chip( preferably xilinx chip ) that I can download my code to.

I have been researching on how to design an FPGA board, but it seems a lot of work. Most of the work done are for big FPGA chips while am looking for something with a lot less pins and logic gates cells
The speed is 564.48kbit\s

This link shows that Manchester Decode can be done with a monostable and a flipflop.
https://www.allaboutcircuits.com/technical-articles/how-to-decode-manchester-encoded-data-using-hardware/

You need to be able to set your RX to 564.48kHz, or half that, depending on what your speed referred to (edge rate or data rate).