[Solved] Small-ish FPGA or CPLD 5V-tolerant ?

[nctnico]

Last time I looked Xilinx XC9500XL series was very cheap and readily available in large quantities from various distributors. For example: Digikey has over 10,000 XC9572XL in various packages/speed grades in stock for immediate delivery. All in all I don't get why the Xilinx XC9500XL dropped from your list.

The XC9500XL series has completely disappeared from Xilinx website.

No, still there under 'other CPLD'

It's support has stopped in ISE8-9 according to andersm.

No, I'm using ISE14.7 for my XC9500XL based designs (the latest ISE version)

Even though it's price is competitive, it requires an external flash.

No, XC9500XL has internal flash!

But what really IS the problem: the XC9500XL is NOT ROHS: "Contains lead / RoHS non-compliant". This alone is a no-no. I'm working on a commercial product.

Where did you get that info from? Ofcourse they are ROHS! Everything non-ROHS which was mainstream has died out over the last decade!
http://www.digikey.com/product-detail/en/xilinx-inc/XC9572XL-10VQG44C/122-1448-ND/966629

[Romain]

Ok, then I guess I was mistaken 
But clicking on the XC9500XL link on Xilinx.com I land here. How is that supposed to make me feel confident?
Besides, none of the documents link work... (Xilinx at it's best).

I found a lot of XC95xxXL CPLDs non-ROHS (in the 9536 range). I assumed they all were.

The link you sent me refers to the following part "Manufacturer Part Number XC9572XL-10VQG44C". The very same part number can be found in Xilinx's Product Discontinuation Notice (PDN) in date of December 2012: http://www.xilinx.com/support/documentation/customer_notices/xcn12011.pdf I'm not really sure what this means...

On Farnell, only 5 references are still in stock in the family: http://uk.farnell.com/webapp/wcs/stores/servlet/Search?catalogId=15001&langId=44&storeId=10151&categoryId=700000004207&sort=P_PRICE&mf=101011&showResults=true&aa=true&sf=432,502,601,731&pf=110202489

The way I see it right now is that I'm not very confident about the XC9500XL lifecycle. I've read it was introduced in 1998?
Maybe there is a way to get a roadmap from Xilinx...?

[nctnico]

If you read the PDN carefully you'll see they are phasing out older versions of parts. This can be due to any number of reasons (maybe moving to a different factory, phasing out non-ROHS parts, etc). Nothing to really worry about as long as there is a replacement (*). True it is an old series and Xilinx goofed up the document links (remove the .uat part) with their website conversion but a distributor like Digikey having many in stock is a good sign that this device is still very popular. Farnell also has over 500 in stock which is rather unusual.

Anyway it never hurts to ask Xilinx about their plans with the XC9500XL series.

(*) In one of my designs I'm using the 4th memory replacement from Micron.

[Romain]

In my attempts of finding a Roadmap for Xilinx's CPLDs, I called my local distributor which will pass over my query to their Xilinx engineer. Stay tuned!

Doing a quick research, I found out that the Xilinx CPLD forum has been archived (sic).
Moreover, the series is considered "Mature", which I believe is the last step before becoming obsolete? : https://forums.xilinx.com/t5/Welcome-Join/Obsolete-CPLD/m-p/687931/highlight/true#M34876

Some packages have already been stopped: http://www.xilinx.com/support/documentation/customer_notices/xcn15006.pdf

I have also posted on Digilent's forum: https://forum.digilentinc.com/topic/2198-xilinx-roadmap-on-xc9500xl-cplds/

[Bruce Abbott]

I'm to re-implement a hard-wired address decode (with lots of 74000) on a board... I'm also considering putting a second STM32F0 just to do the address decoding...

10 Address lines... 2 buses of 8 bits... 5-8 control signals... Different addresses need to be decoded, and the data latched, so the microcontroller has time to read it... off-load the microcontroller from watching the 5MHz bus all the time. One good thing is that the data rate is quite slow (about 1kHz, no more)... the bus I'm interfacing with is 5V

to save place and allow upgradability, I'd like to do that in programmable logic.

I'm looking for something very small, and most importantly very cheap (sub $2)...

I'm not very confident about the XC9500XL lifecycle... the product will be available for at least the next 5 years...

TTL ICs are still cheap enough to not justify programmable logic when the operation only needs a few 10s of them

You want to replace an existing TTL address decoding circuit with a decoder and latch that frees up the microcontroller from polling the bus. The bus is 5V, but the micro is an STM32F0 running on (<=)3.3V, right? Is the MCU replacing a legacy TTL device?

10 address lines, 8 data, 5-8 control, 5MHz, 5V, TTL. What system bus is this?

If 10+ TTL IC's are so cheap (even though they must take up quite a lot of PCB area) then why do you need something 'very small' and more importantly 'sub $2'? Was the original device too bulky and expensive for your market?

You seem to be very concerned about whether the CPLD you choose will be available in 5 years time, and having 10,000 available now is not assuaging your fears. Does this mean you are only doing small production runs, and don't want to stockpile chips?

The existing design used hard-wired logic and (I assume) worked OK, so why do you want it to be 'upgradable'?

What is the purpose of your device?

Sorry for all the questions, but if we knew what you were actually trying to do it might help...

The ispMACH4000ZE looks good on paper...

IMO this is the only CPLD that will meet all your requirements, because:-

1. Older devices might not be around in 5 years time.
2. Using a low I/O voltage device with level shifters will take up more space and raise the cost.
3. No other modern CPLD family (that I know of) is truly 5V tolerant.

There is one other solution you might consider - Cypress PSOC-4200. Runs on 5V, has internal CPLD, and I/O pins can be configured for latched input (ideal for operating as a 'slave' device on a microprocessor bus).
 
 

[Scrts]

Alteras' relatively new MAX V family can support 5V:
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/pt/max-v-product-table.pdf
Same for MAX II:
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/pt/max-ii-product-table.pdf

[Romain]

Hi Bruce, and thanks for taking the time to answer me.
Here are the answers to your questions

You want to replace an existing TTL address decoding circuit with a decoder and latch that frees up the microcontroller from polling the bus. The bus is 5V, but the micro is an STM32F0 running on (<=)3.3V, right? Is the MCU replacing a legacy TTL device?

The micro actually has 5V tolerant inputs. The micro is already fully functional in the actual design.

10 address lines, 8 data, 5-8 control, 5MHz, 5V, TTL. What system bus is this?

It is a MC68000 system bus. Luckily I'm only interfacing to a portion of this bus, so I only need to watch some specific address lines, and not the whole bus! Basically, it's "sniffing" data from an old system and forward them to a new IT system through this STM32 and then a MCU connected through UART where the data can be interpreted on a Linux computer.
The MC68000 is 5V, and the trigger/latch logic based on the 7400 already works a treat!

If 10+ TTL IC's are so cheap (even though they must take up quite a lot of PCB area) then why do you need something 'very small' and more importantly 'sub $2'? Was the original device too bulky and expensive for your market?

A redesign of a working circuit does take a lot to reconsider. But in a nutshell, it is "worth it" if the alternative is: smaller AND cheaper AND more flexible.

You seem to be very concerned about whether the CPLD you choose will be available in 5 years time, and having 10,000 available now is not assuaging your fears. Does this mean you are only doing small production runs, and don't want to stockpile chips?

Exactly

The existing design used hard-wired logic and (I assume) worked OK, so why do you want it to be 'upgradable'?
What is the purpose of your device?[/quite]
The "upgradability" would allow to simply reconfigure the address decode to be able to intercept more messages in the future with the same design (either for extended features, or for a compatibility with similar 'but slightly different' systems).

Sorry for all the questions, but if we knew what you were actually trying to do it might help...

The ispMACH4000ZE looks good on paper...

IMO this is the only CPLD that will meet all your requirements, because:-

1. Older devices might not be around in 5 years time.
2. Using a low I/O voltage device with level shifters will take up more space and raise the cost.
3. No other modern CPLD family (that I know of) is truly 5V tolerant.

1. You're absolutely true, and this was my biggest fear. In this case, what am I gonna do? Redesign a board to end up in a bottleneck I could have simply avoided by doing nothing? Not so smart...
2. This could be discussed, because TTLs may not exist in the smallest packages (QFN), where a CPLD and 2 level-shifters could bring drastically bring down the IC count.
3. Thanks! I was expecting that unfortunately...

There is one other solution you might consider - Cypress PSOC-4200. Runs on 5V, has internal CPLD, and I/O pins can be configured for latched input (ideal for operating as a 'slave' device on a microprocessor bus).

That's a very interesting alternative! I'll have a look at their datasheet and see how the Smart IO can be used to do address decoding.

Thanks again

[Romain]

Just a quick update to let you know that the PSoC solution has been approved for the project! 
Thank you very much Bruce for your suggestion! It was actually my first time with Cypress, and I'm delighted with their IDE and support! There are tons of code example, which makes the use of the chip as easy as 1 2 3.
The best in all of that? The chip costs less than $2! ($1.9 to be exact).

I decided to go for a PSoC 4200 (CY8C4245LTI-M445), and the decode logic is implemented in what they call the 'UDBs' (a bunch of ultra-small CPLDs).
Link for reference: http://www.cypress.com/products/32-bit-arm-cortex-m0-psoc-4200-programmable-digital-blocks

Marking this topic as Solved!
Thanks!

[nctnico]

Thanks for the update! It is always useful to know what solution was choosen in the end 

[c64]

I don't get it why the MAX ii is called "5v compatible". You need to power it with 3.3v supply, and use diodes and resistors on each pin. But you can do exactly the same with a modern 3.3v FPGA, can't you?

[EverydayMuffin]

Interesting choice with the PSoC, I don't hear of many people using UDBs on PSoC.

I see the most UDBs on PSoC 4 in on the PSoC 4200L with 8 UDBs. (I think more are available with PSoC 5 and PSoC 6).

Is there a way to work out the amount of logic elements (say LUT4) a UDB is equivalent to?

[Romain]

This bus address decoder implemented in the CY8C4245AXI-483 gives the following resource usage.

I'll let you do the maths

[hli]

Is there a way to work out the amount of logic elements (say LUT4) a UDB is equivalent to?

One UDB contains 8 'conventional' MacroCells, so the 4 UDBs in the CY8C4525 contain 32 MCs. (the largest PSoC5s have 24 UDBs, so 192 MCs). But each UDB also contains a so called 'DataPath' which is more like a programmable 8bit-ALU (its 2 accumulators, 2 data registers, 2 FIFOs and one ALU which can compare, shift or calculate). When you manage to master them 24 UDBs can achieve quite a lot (quite a number of the PSoC5 'peripherals' are implemented as UDBs).