The Altera software is just really really good. That's all. It is easy to draw a schematic , compile and download.
CPLD and FPGA is nothing to be afraid of. They are just a massive drawer filled with 74xx chips ... ( actually massive drawers with LUTS (look up tables : in essence a AND/OR matrix) and flipflops )
all you do is specify how to connect them , just like you would do with real chips. Altera gives you a library with almost and 74xx series imaginable as well as a massive list of other functions.
If you think schematic is powerful : wait until you dig your heels into synthesis languages such as Verilog-2005. You will be writing a logic system faster than you can draw it in a schematic.
module counter(input clk,clear,load,direction,enable,
input [3:0] data_in,
output [3:0] count_out)
always @posedge(clk) begin
if(enable) begin
if (direction) count_out <= count_out +1;
else count_out <= count_out -1;
end;
else begin
if (load) count_out <= data_in;
end;
if (clear) count_out <=0;
endmodule
endmodule
This is a 4 bit up/down parallel loadable ,resettable counter ( kinda like a 74193). For ease of following, all signals are active high.
simplified, here is what happens :
Whenever there is a rising edge on CLK ( posedge(clk) this lump of code fires.
First it will check the 'enable' pin.
If enable is high it will check the Direction pin and, depneding on its state , count up or down.
If enable is low, it will check the load pin. if that one is high it will perform a parallel load.
As a last rule it will check the CLEAR pin. if that one is high it will reset the counter to zero ( irrespective of what previous instructions decided to do. The statement closest to the 'endmodule' that evaluates is what is executed. This is inheritent in both Verilog and VHDL standards.
now, want to make this a 32 bit counter ? ( with 74193 you will need 8 of them plus some glue logic ) simple change the definition of the data_in and count_out
input [31:0] data_in,
output [31:0] count_out