I want to demodulate all the FM stations simultaneously using an FPGA and SDR. For this I need to implement around 10 receivers each tuned to a different frequency.
The baseband signal coming in will be 20MSPS I and Q and will include all the stations.
In each receiver, the baseband signal is multiplied by the complex sinusoid to shift the desired channel to 0Hz. This will already take up all the multipliers in the FPGA, so any filtering afterwards can not use hardware multipliers. After the multiplication I need to filter and decimate the signal to +/-80kHz bandwidth and sample rate around 400ksps.
Normally I would use the polyphase convolution for something like this, since the decimation factor is high (50), but to do so a hard multiplier is needed since we aren't multiplying by constants anymore (the whole point of polyphase fir is so that you don't need a multiplier for every coefficient, which means the multipliers now are dealing with dynamic coefficients read from a rom). There aren't enough hardware multipliers remaining so this is ruled out.
Cascading many direct form FIR filters (each filter decimates by 2) helps somewhat, but since a sharp rolloff is needed the final filter still has to be of fairly high order (~64), which would consume quite some area. The filter should be as small as possible so the maximum number of receivers can be put in the FPGA.
IIR filters also seem a good option, but I'm not sure if the nonlinear phase over frequency will cause noticeable distortion with FM?
There are 16 total multipliers in the FPGA, but the frequency shifter requires complex multiplications so will take 4 multipliers. The multiplier will have to be multiplexed between the 10 receivers (using shift registers), so the multiplier will be running at 200MHz. The 12 remaining multipliers can implement 6 complex-valued polyphase filters, not quite enough.
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