Space Grade FPGAs

[rakeshm55]

Hi,
i would like to explore space grade FPGA usage.....
What are the precautions to be taken to work on space grade fpgas?? I prefer to go with Virtex-5QV series ....

is the design flow similar to normal xilinx FPGAs??.... I am new to TMR and data scrubbing ..... Will TMR severely reduce the Logic cell usages of FPGA.....

Is there in restriction on using different resoucrces of FPGA like block RAM, DSP slices etc....

Please advice....

[6thimage]

The design flow is identical to normal FPGAs - the tools are identical because the space grade and non-space grade FPGAs have the same functionality, they just have different silicon. The space grade parts are certified to be able to stand a certain TID (level of radiation), that is the only difference.

But, this doesn't mean that companies developing for space grade FPGAs will use the same design flow, they will often have similar flows to safety critical designs - where the design is tested to a higher degree, with the tools providing assurance that the design is not modified during layout and routing.

This does mean that you can spend time developing for space, but targeting commercial grade FPGAs, which is a lot cheaper until very late in the product design.

There are some additional steps if you use certain FPGA features - I have a colleague who is using partial reconfiguration in Virtex FPGAs to allow for partial recovery of a design when an error is detected, which requires a certain type of bit file.

TMR repeats the logic three times and adds some voting logic, so if you use TMR on all of your design, it will take up 3x the logic cells, plus a little bit. A large downside to this is that it can significantly impact the timing.

Why would there be a restriction on different resources?

What are you planning to build? Are you jumping in the deep end with trying to target space - a lot of companies would be more impressed with well designed non-space projects than a poorly made space project.

[rakeshm55]

My aim was to build re configurable (sdr) waveforms into a virtex Fpga... client would like to have the development done on a space grade FPGA....since my exposure is to xilinx part I decided to choose space compliant FPGAs from xilinx...

[ehughes]

I am in the middle of a design targeting a Space Application.

1.)   Your only option is the a small number of V5 and V4 parts.  The V5 parts have a bit more resources.
2.)   The internal BRAMs are NOT rad hard
3.)   Designing in TMR is important but you also have to consider *where* you TMR.   I.E.   Do you do it at a Macro level (high level blocks) or at a lower level.
4.)    To get access to the tools,  you need to be using V13.2 of ISE.    You need to get ahold of your local FAE who can put you in touch with a representative from Xilinx's Space Support group.      You will need to some paper work to get a hold of a special patch/overlay to place and route against the space devices
5.)   We are using the OPenSparc (XUPV5) for benchtop work.  It is fairly close to the space part (which is an oddball in terms of the logic,etc. it doesn't map to any specific normal V5 Part)
6.)   The Key to a successful project is proper engineering governance.   A proper design takes years.
7.)   The project funding should have a minimum of 6 zeros to have any hope of doing a proper design. 7 zeros is much better.

Believe it or not,  radiation is *NOT* the biggest challenge of a space design.    It is dealing with vibration at launch and dealing with any heat once you are up there.  Unlike popular movie dramatization, space is not cold like Antartica where you turn into an instant ice block..   It is a vacuum and you have to move heat via conduction to the outer hull and then radiate from there.  There is no convection in space.  I.E. a heat sink and fan does nothing.

Also,  make sure you are ready to spend between $30 to 40k per device and you have to properly mount a column grid array.   You will probably have 60k in getting a *single* board made.    Assembly should only be done in a clean environment (rguys in bunny suits).  There are only a few places in the US who are approved by Xilinx to mount the device.

If you need external memory,  cypress has parts starting at 30k....

Good Luck...    Get ready to simulate for a few years.

[mikeselectricstuff]

3.)   Designing in TMR is important but you also have to consider *where* you TMR.   I.E.   Do you do it at a Macro level (high level blocks) or at a lower level.

..and presumably you need to take care that the  toolchain doesn't optimise out the redundancy...

[rakeshm55]

If i choose a Radiation Hardened  XQR5VFX130 can I do away with TMR and scrubbing??.....
is  occasional  power cycling suffice??....

Also for discrete components like decoupling can I use smd part (capacitors etc)...is it mandatory to use thru hole parts to overcome excessive vibrations...

[nfmax]

7.)   The project funding should have a minimum of 6 zeros to have any hope of doing a proper design. 7 zeros is much better.

Leading zeros don't count! 

[KJDS]

If i choose a Radiation Hardened  XQR5VFX130 can I do away with TMR and scrubbing??.....
is  occasional  power cycling suffice??....

Also for discrete components like decoupling can I use smd part (capacitors etc)...is it mandatory to use thru hole parts to overcome excessive vibrations...

Whilst I know nothing about FPGAs, I do know some about space design. The answer is, it depends. There is plenty of SMD in space, but everything will need to be derated, life expectancy designed in, as will a worst case analysis and assembly processes will all need to be space level qualified. Parts level qualification is application dependent, but usually requires as a minimum LAT of high grade parts.

[Scrts]

It is a vacuum and you have to move heat via conduction to the outer hull and then radiate from there.  There is no convection in space.  I.E. a heat sink and fan does nothing.

That's actually very interesting. How do you deal with heat dissipation?

[KJDS]

It is a vacuum and you have to move heat via conduction to the outer hull and then radiate from there.  There is no convection in space.  I.E. a heat sink and fan does nothing.

That's actually very interesting. How do you deal with heat dissipation?

Using conduction. Careful design, so that hot parts have a short thermal path to the housing, and from there a path to the outer hull. The expected operating temperature of every component in a satellite is calculated.

[albert22]

An example of design for redundancy can be this:
http://www.gaisler.com/index.php/products/processors/leon3ft
Where you can find the features of a radiation hardened leon3  SPARC V8 processor that could be implemented in a RTAX2000S.

[Bassman59]

My aim was to build re configurable (sdr) waveforms into a virtex Fpga... client would like to have the development done on a space grade FPGA....since my exposure is to xilinx part I decided to choose space compliant FPGAs from xilinx...

You should ask your local FAE to give you a quote for the Xilinx space-grade FPGAs. I guarantee that after you read the quote, you will pick your jaw up off the floor and then you will reconsider the whole project.

[Bassman59]

3.)   Designing in TMR is important but you also have to consider *where* you TMR.   I.E.   Do you do it at a Macro level (high level blocks) or at a lower level.

..and presumably you need to take care that the  toolchain doesn't optimise out the redundancy...

Synplify Pro does proper TMR. It is also ridiculously expensive.

Having said that, if your target is a Microsemi device, their tools bundle in a version of Synplify Pro which targets only their devices, and it does TMR. If the target device has TMR in hardware, Synplify "knows" about it and will Do The Right Thing.

[ehughes]

From the questions you are asking, make sure your client understands the true cost of designing for space.   

1.) We are talking minimum 10's of millions from concept to something that could be launched
2.).  1 person cannot do the job.   You will need to involve people versed in thermal design, vibration/ modal analysis, a manufacturing team that understands QML,   some to manage the engineering governance, etc.
3.   You will need real simulation software (comsol multiphysics)
4.).  Do you know the launch platform?   
5.). Is there a complete formal specification for the platform and payload hardware?

It takes *years* of planning and design for proper space hardware.   If your client isn't already talking to people who have a background in this design work,   it sounds like this project is beyond them.   Not to be a Debbie Downer but DO NOT take this work if your client doesn't understand the cost and effort involved.


If the goal was to simply target the space grade parts for warm and fuzzies,   just proceed with a comparable commercial part.  Just keep in mind the rad hard parts will be slower.   

FYI...  You still need TMR/error checking with rad hard.   They are better but not perfect.

Here is another metric.   Measure the hours to write the hdl for the behavioral code.  Then assess what you have into the simulation and test code.   If that ratio isnt at least 10:1 (test benches to behavioral code),  you are not testing enough.   The test code is often much more complicated than the logic itself.   Every hour of code development should have 10 of simulation development.


Good luck. Space is unforgiving.

[Rasz]

From the questions you are asking, make sure your client understands the true cost of designing for space.   

1.) We are talking minimum 10's of millions from concept to something that could be launched
2.).  1 person cannot do the job.   You will need to involve people versed in thermal design, vibration/ modal analysis, a manufacturing team that understands QML,   some to manage the engineering governance, etc.
3.   You will need real simulation software (comsol multiphysics)
4.).  Do you know the launch platform?   
5.). Is there a complete formal specification for the platform and payload hardware?

It takes *years* of planning and design for proper space hardware.   If your client isn't already talking to people who have a background in this design work,   it sounds like this project is beyond them.   Not to be a Debbie Downer but DO NOT take this work if your client doesn't understand the cost and effort involved.


If the goal was to simply target the space grade parts for warm and fuzzies,   just proceed with a comparable commercial part.  Just keep in mind the rad hard parts will be slower.   

FYI...  You still need TMR/error checking with rad hard.   They are better but not perfect.

Here is another metric.   Measure the hours to write the hdl for the behavioral code.  Then assess what you have into the simulation and test code.   If that ratio isnt at least 10:1 (test benches to behavioral code),  you are not testing enough.   The test code is often much more complicated than the logic itself.   Every hour of code development should have 10 of simulation development.


Good luck. Space is unforgiving.

or just shoot a lot of 'cellphones' up with full understanding of shorter lifespan and lower reliability (like Planet Labs)

[UConn94]

Even though Xilinx may be preferred, in this type of environment, Microsemi(formerly Actel) should be seriously considered - especially for their SEU immunity, and the Igloo2(low power) devices boasts of hardened memory subsystem.

Another benefit of Microsemi devices, free license(renew annually free) to use their Libero SoC IDE with Synopses Pro and Modelsim.

With Microsemi devices, when programmed, they are instant-on at power up, there is no external memory device to upload the firmware, it is all built-in.

[gael]

Check also the new Microsemi RTG4 devices: http://www.microsemi.com/products/fpga-soc/radtolerant-fpgas/rtg4

[Avien]

Check also the new Microsemi RTG4 devices: http://www.microsemi.com/products/fpga-soc/radtolerant-fpgas/rtg4

Those do not have flight heritage so I would stay away from them (at least for now), ESA and NASA will probably decline usage of them.

I would stick with other Microsemi products, their industrial and military stuff based on flash is pretty radiation tolerant ( I have found a research which proves that industrial FPGA is slightly worse than rad hard part).

[fonograph]

How much does Microsemi RTG4 cost?

[Daixiwen]

They don't give prices publicly so you will have to ask for a quote but a rough idea is *a lot*. And you also need a platinum license to have the privilege of actually developing on the thing.
To those that used Actel/Microsemi products before, be careful, they changed their licensing rules recently and several targets that were previously covered by the free license now require a paid annual license: https://www.microsemi.com/products/fpga-soc/design-resources/licensing.
We have a couple of development kits here that we can't use with the latest Libero software unless we pay.

I've never used the radhard Xilinx parts but we have used Microsemi FPGAs and as previously said the tools (or in some cases, the FPGA itself) already take care of the redundancy for you. IIRC most Microsemi parts are also more tolerant than the Xilinx ones, but it all depends on how much radiation you must tolerate.
And don't forget that when working on a space project, you'll spend 99% of your time writing documentation, and 1% doing actual development.

[amyk]

http://www.mouser.com/ProductDetail/Microsemi/RTG4-DEV-KIT/ Nearly $20k for the dev kit.

[Daixiwen]

And that's with a PROTO part. It's cheap compared to the flight version.