Spartan 7...

[ehughes]

There will be some official news in a week or two.  I got to see some of the advanced sales info.

-the early announcement date was to solidify commitment to the low end market.   Around the time of the original announcement,Intel acquired Altera.   Intel has stated that the focus will be on the data center.   The low end market is not a focus for Intel. 

-The S7 is essentially an Artix-7 without the transceivers.   Will be cost comparable to the S6.   I could not get hard numbers.....

- There will be some more lower end Artix 7 devices announced.

- It will be sampling (engineering) in March of 2017.   General availability in 2018.   Use Artix series for now.

-S7 is Vivado only.  S6 will be supported for another 10 years.   ISE will be patched to work with Windows 10 for the S6

-The QFP ship has sailed.   There is no real demand for QFP in the market.  S7 will be BGA only - same packages as the Artix 7

-there will be some lower end single core Zynq devices announced soon.

[KE5FX]

Eh, plenty of people solder BGAs by hand.  Preheat board, apply hot air to top of chip, wait until it centers itself, withdraw hot air, turn off preheater.

[KE5FX]

You're probably better off not adding any solder paste at all.  Just put a bunch of flux on the pads and let the solder balls adhere on their own.

[helius]

As he said, the problem with that is that the chip will not have the thermal and mechanical relief of fully formed ball fillets that it is designed for.
From my limited experience, it is possible to diagnose some BGA problems using a borescope, so X-ray inspection may or may not be necessary.

[KE5FX]

Your dentist may also be up for it.  Dentists are almost universally gadget freaks.

[KE5FX]

As he said, the problem with that is that the chip will not have the thermal and mechanical relief of fully formed ball fillets that it is designed for.
From my limited experience, it is possible to diagnose some BGA problems using a borescope, so X-ray inspection may or may not be necessary.

None of these suggestions are going to fly in a six-sigma facility, but at the end of the day, if you just want to get a prototype working... whatever works, works.

[mark03]

Back to the original point, what is Xilinx's answer to "Why not QFN?"

I have heard the argument "We have N I/Os on a chip of that size, and what crazy person *wouldn't* want every single one of them brought out to the package?"  I don't understand that attitude, but, presumably they know their market.

[janoc]

Back to the original point, what is Xilinx's answer to "Why not QFN?"

Were there ever any Spartans in QFN? I recall only QFP for the low end low pin devices and then BGAs.

It sucks though - a hobbyist wanting to use an FPGA will be stuck with either premade devboards, obsolete parts or both. I guess I should have another look at the Lattice chips instead

[daveatol]

I can solder BGA, and I work manually down to 0.4mm pitch WLCSP. I also do home made die bump flip chips (we have sputter equipment to titanium/nickel/silver/gold plate aluminum bonding pads).
The problem is yield. With pre-tinned board I have 80%+ yield if rework is allowed, but with stencil printed, non-pre-tinned ENIG boards I have terribly bad yield. Small paste dislocation can create shorts.



This is a perfect solder paste print, yet it still resulted in shorts due to manual device placement error.

Those pads look like they have too much solder on them. (speaking from zero practical experience). What happens if you reduce the stencil apertures?

[langwadt]

I can solder BGA, and I work manually down to 0.4mm pitch WLCSP. I also do home made die bump flip chips (we have sputter equipment to titanium/nickel/silver/gold plate aluminum bonding pads).
The problem is yield. With pre-tinned board I have 80%+ yield if rework is allowed, but with stencil printed, non-pre-tinned ENIG boards I have terribly bad yield. Small paste dislocation can create shorts.



This is a perfect solder paste print, yet it still resulted in shorts due to manual device placement error.

Those pads look like they have too much solder on them. (speaking from zero practical experience). What happens if you reduce the stencil apertures?

yeh looks like full coverage, that is too much

[hamster_nz]

A friend tweeted me that documents are available that include Spartan 7:

http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf

Packaging option is 144-pin TQFP with 23k logic cells, 80 DSP blocks, and about 200kB of block RAM.

[MagicSmoker]

Those pads look like they have too much solder on them. (speaking from zero practical experience). What happens if you reduce the stencil apertures?

Then 0402 parts will suffer from insufficient solder paste and won't have side solder fillet.
The proper way is to reduce BGA stencil opening size, but then I need better stencil quality and printing equipment, which I have access to neither.
Anyway this is only a prototype board. The design will be ASICed after all.

We're kind of veering off into the weeds here, but another way to deposit less paste overall is to use a thinner stencil. I also think that the print looks good, but that there is too just too much paste present.

[hamster_nz]

A mashup of http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf and http://www.xilinx.com/support/documentation/data_sheets/ds189-spartan-7-data-sheet.pdf

[ali_asadzadeh]

They just release some Documentation, why they have so little LUT's!? compared to SP6! and the specs does not seems something impressive.

[ali_asadzadeh]

The only supprising thing could be their prices! Already SP6 have 150K LUT's