Author Topic: spartan6 lx9 interface with adc (AD9238)  (Read 2108 times)

0 Members and 1 Guest are viewing this topic.

Offline alireza7Topic starter

  • Regular Contributor
  • *
  • Posts: 102
  • Country: us
spartan6 lx9 interface with adc (AD9238)
« on: November 19, 2017, 09:37:20 am »
hi
i want to clock a AD9238-65 which is a 65mhz adc with a spartan6 XC6SLX9-2TQG144I.
AD9238-65 is a dual channel adc. if i clock these pins  ADC_MUX and ADC_CLKA and ADC_CLKB with the same signal i can read both channel A and channel B on single portA and there is no need to connect port B of the adc to the fpga and use less IO pins of fpga.

my question is whether i can connect a single pin of fpga to these there pins of adc ? is a single pin of fpga able to drive these pins in 65mhz ? or i need some buffer between?
how can i figure it out? i checked spartan6 datasheets for DC AC Charactristic of io pins but it was confusing for me and i couldn't figure it out.
« Last Edit: November 19, 2017, 06:52:41 pm by alireza7 »
 

Offline alireza7Topic starter

  • Regular Contributor
  • *
  • Posts: 102
  • Country: us
Re: spartan6 lx9 interface with adc (AD9238)
« Reply #1 on: November 19, 2017, 09:54:59 am »
here is the input characteristic of adc:
« Last Edit: November 19, 2017, 06:53:11 pm by alireza7 »
 

Online Someone

  • Super Contributor
  • ***
  • Posts: 4510
  • Country: au
    • send complaints here
Re: spartan6 lx9 interface with adc (AD9238)
« Reply #2 on: November 19, 2017, 11:49:12 pm »
my question is whether i can connect a single pin of fpga to these there pins of adc ? is a single pin of fpga able to drive these pins in 65mhz ? or i need some buffer between?
how can i figure it out? i checked spartan6 datasheets for DC AC Charactristic of io pins but it was confusing for me and i couldn't figure it out.
First order estimate is from the impedance of the pins you will drive, compared to the current capabilities of the drive pin. Then you can get more accurate with simulations:
https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models/hspice-and-eldo-models/spartan-series-fpgas.html
https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models/ibis-models/spartan-series-fpgas.html
 

Offline nctnico

  • Super Contributor
  • ***
  • Posts: 26755
  • Country: nl
    • NCT Developments
Re: spartan6 lx9 interface with adc (AD9238)
« Reply #3 on: November 20, 2017, 12:36:17 am »
AFAIK you can set Xilinx pins to 12mA drive current. You'll need to charge and discharge the capacitance of the pins and traces fast enough. You can make a ball-park estimate by modelling the pin as a constant current source and the load as a capacitor. Say you have a total capacitance of 8pf (4pf input and 4pf trace) and you have a difference of 3.3V then 12mA will charge/discharge that in 2.2ns t=(C* voltage swing)/Idrive. 65MHz means a 15.3ns period so 7.7ns high and 7.7ns low. The clock net will need some termination (33 Ohm in series at the FPGA pin for example) to prevent excessive ringing.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline simmconn

  • Regular Contributor
  • *
  • Posts: 55
Re: spartan6 lx9 interface with adc (AD9238)
« Reply #4 on: November 20, 2017, 05:49:26 am »
Spartan6 has no problem driving LVCMOS at 65MHz. I can even use 6mA drive strength without termination for two loads if the trace length is short enough.
Since OP is thinking about DDR mode, 65MHz is about the frequency where the round trip delay (IO pad output delay + input delay + 2x PCB trace delay) starts to play a role here. You'll probably be split among
1) using the feedback clock from the clock output pad to latch the input data,
2) use a separate clock feedback pin to latch the input data or
3) even fancier clock delay compensation schemes (such as adjustable delay from DCM).
 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf