Spartan6 has no problem driving LVCMOS at 65MHz. I can even use 6mA drive strength without termination for two loads if the trace length is short enough.
Since OP is thinking about DDR mode, 65MHz is about the frequency where the round trip delay (IO pad output delay + input delay + 2x PCB trace delay) starts to play a role here. You'll probably be split among
1) using the feedback clock from the clock output pad to latch the input data,
2) use a separate clock feedback pin to latch the input data or
3) even fancier clock delay compensation schemes (such as adjustable delay from DCM).