Square-wave synthesis with high frequency resolution

[mark03]

This might be a stupid question, but I've googled and can't find an answer, or perhaps I don't know the correct key words.  Suppose you need to generate a square wave of precise yet variable frequency, so you can't just divide from a higher-speed clock.  As an example, take WSPR signal generation; this is a low-bit-rate, highly coded FSK modulation used in ham radio, with tones 1.4648 Hz apart.

Everyone knows how to do this for sinusoids using direct digital synthesis (DDS) with a DAC, look-up table, and various interpolation trade-offs.  Clearly one could use a DDS followed by a squaring circuit, but I would like to know if there are clever digital architectures (delay lines?) for getting this directly out of an FPGA.

The WSPR example has actually been done in software on a Raspberry Pi:
http://rheslip.blogspot.com/2013/10/wspr-with-raspberry-pi.html
I don't think the square-wave output is particularly accurate on a cycle-to-cycle basis, but it was being used to drive a class-E amplifier circuit, which probably helps smooth out the extreme phase noise of the RPi digital output.

[uChip]

You can use a DDS circuit.  Build one in your FPGA.  Just change the lookup table to be a square wave rather than a sine.

Alternatively, depending on the accuracy required you can use a down counter.  Starting with a 10 MHz clock you would have a resolution of 100 nS.  1.4648 Hz is 682.687 mS.  0.1% of that would be 682.687 uS.  Again what accuracy do you need?

[mark03]

You can use a DDS circuit.  Build one in your FPGA.  Just change the lookup table to be a square wave rather than a sine.

This would be equivalent to a simple counter.  Your edges can still only be placed onto a quantized time scale with steps equal to 1/f_clk.

Alternatively, depending on the accuracy required you can use a down counter.  Starting with a 10 MHz clock you would have a resolution of 100 nS.  1.4648 Hz is 682.687 mS.  0.1% of that would be 682.687 uS.  Again what accuracy do you need?

Sorry, I should have further specified "at high frequency."  To borrow the WSPR example again, the challenge is generating square waves at ~ 10 MHz with a frequency resolution of ~ 1 Hz.  A naive approach based on integer division would require a clock in the terahertz region.  Clearly not an option.

My question really boils down to whether there are approaches which reduce complexity and/or power over the obvious DDS-followed-by-a-comparator.

[bktemp]

It could be possible to make a DDS with finer steps using delay lines:
On every clock transition use the DDS LSBs to determine the exact timing for the clock edge and delay the clock edge using delay lines (LUTs in series).
I have never done it, but it should be possible. Many microcontrollers achieve GHz PWM resolution with only using ~100MHz by adding finer steps using delay lines.

[rfeecs]

Use a PLL.  No FPGA needed.

To quote the Wikipedia article on WSPR:

Usually a WSPR station contains a computer and a transceiver, but it is also possible to build very simple beacon transmitters with little effort. For example a simple WSPR beacon can be built using the Si570.[4] The Raspberry Pi can also be used as WSPR beacon.

Si570 is a PLL/Synthesizer with a 38-bit tuning resolution of .09 ppb:
https://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf

Looks like 1.4684 = 12000 / 8192.  That might also make things easier.

[tggzzz]

How fast do you need to change/modulate the output frequency? Do you need to change the phase? What jitter or phase noise is acceptable?

Different generation techniques have different advantages and disadvantages.

[mark03]

How fast do you need to change/modulate the output frequency? Do you need to change the phase? What jitter or phase noise is acceptable?

I would say my ultimate interest is in direct amplitude/phase modulation into a class-E transmitter.  This is where you modulate the FET drain voltage as sqrt(I^2+Q^2) with a switch-mode supply, and drive the FET gate with the phase-modulated square-wave carrier.  This can only work with relatively narrowband signals, 1% fractional BW probably, 10% fractional BW probably not.

WSPR is at the ridiculously easy end of this spectrum, with a signaling rate of 1.4648 baud.  I am curious to find out if the approach is tenable for other complex modulation in kHz or larger bandwidths at HF (3-30 MHz).  I don't know the necessary phase-noise spec.  I imagine the easiest way to find out would be to run some experiments.

I would like to know how Silabs' clock generators like the Si570 work.  Is their technology widely understood?  Where could I read up on it (besides Silabs data sheets and app notes)?

[rfeecs]

I'm not sure about the specifics of the Silabs parts, but the search term would probably be Fractional-N Synthesizer.

For the class-E example, it seems you just need a phase modulator and a local oscillator.  The local oscillator would be fixed and not related in frequency to the I and Q.

I guess you are trying to avoid the phase modulator and directly digitally generate the phase modulated signal?

[mark03]

I was hoping for an all-digital or mostly-digital solution.  Analog will have to factor in somehow though as even the delay-line approaches cannot approach the necessary time resolution.

I looked more closely at Silab's marketing material and see they are using a mostly analog approach (nested PLLs), presumably with a comparator as the last step to get the digital output.  I wonder how a DDS+comparator approach would compare in terms of phase noise (with the DDS mostly in the FPGA).

This patent looks interesting:
http://www.google.com/patents/WO2014109974A9?cl=en
but I haven't found a version with diagrams.  Not sure what a "gearbox" is in this context.

[langwadt]

in the "long" term using the MSB off a DDS will be as accurate in frequency as you have bits in the accumulator,  it is really no different than a single bit DA converter

[Someone]

I was hoping for an all-digital or mostly-digital solution.  Analog will have to factor in somehow though as even the delay-line approaches cannot approach the necessary time resolution.

Delay lines are going to be close to the limit of whats achievable from a noise perspective, you could roll your own in logic if you need more precision. The reference design is "All Digital VCXO Replacement" from Xilinx.

[danfo098]

FPGA's usually have built in analog PLL's. What about using them to clean up the jitter/phase noise from the DDS/counter?

To do this just route the MSB of the DDS/counter to an output pin (use fast output buffer/Xilinx IOB) that is next to a clock input pin on the FPGA and then this is connected to the internal analog PLL. Then set the PLL loop filter to the lowest bandwidth to clean up the jitter. Altera FPGA's use to have 4 of these PLL's so the process can be repeated for further cleaning.

I haven't tried this but I think it should work, not sure if the PLL can lock on to the very jittery input signal though? Altera PLL's min input frequency is 5 MHz I think so to get 10 MHz you could add a 2x multiplier in the analog PLL and generate 5 MHz with your DDS.

To get a really high frequency resolution use a counter with like 64 bits.

[mark03]

Thanks everyone for the ideas.  Clearly I need to learn more about FPGA PLLs, though it seems hard to beat a DDS in terms of flexibility and simplicity.

[danadak]

NCO ...... https://en.wikipedia.org/wiki/Numerically_controlled_oscillator

http://ww1.microchip.com/downloads/cn/AppNotes/cn561389.pdf

Regards, Dana.

[Someone]

NCO ...... https://en.wikipedia.org/wiki/Numerically_controlled_oscillator

http://ww1.microchip.com/downloads/cn/AppNotes/cn561389.pdf

Regards, Dana.

An NCO is not going to come close to the resolution the OP is asking for, this needs a much more sophisticated approach. Xilinx have the whole solution offered as part of their IP package.

[mark03]

Thanks Someone, I did skim that Xilinx app note and it looks promising.  A bit beyond me at the moment as I'm just starting out with FPGAs.  It wasn't clear to me how low this could go in frequency--obviously the intent is GHz clocks rather than tens of MHz.  And also, for a given center frequency how many ppm +/- can be achieved.

The ordinary 7-series clock tiles have a similar dynamic phase-adjust feature, although they are limited to single-step phase adjustment in each phase-adjust period.  Someone on the Xilinx forums ran the numbers which come out to max +/- 500 ppm frequency offset, a bit less than I was hoping for but certainly enough to match VCXO tuning range.  The GT_ transceiver IP seems quite a bit more capable.

It's too bad they don't offer any transceivers on the most convenient Artix package (fat-pitch 256 pin).  You have to go to 484 pins (!) or impossibly tiny pitches to get one.  No matter though, I'm not ready to sit down and start designing... just learning at this point.

[dannyf]

I would like to know if there are clever digital architectures (delay lines?) for getting this directly out of an FPGA.

to load it up with a square wave table (vs. a sine table).

Or to use PLL chips - TI and ONSemi have a bunch of them.

[Daving]

Sorry, I should have further specified "at high frequency."  To borrow the WSPR example again, the challenge is generating square waves at ~ 10 MHz with a frequency resolution of ~ 1 Hz.  A naive approach based on integer division would require a clock in the terahertz region.  Clearly not an option.

My question really boils down to whether there are approaches which reduce complexity and/or power over the obvious DDS-followed-by-a-comparator.

You need a 10MHz clock and be able to fine tune it down to 1 hz.

So you need a reference clock that is better than 10 part per billion if you want to set your clock to 10,000,001 and have an error of 0.1 hz.  That's oven controlled oscillator territory.

Is this the requirement you need, or the control you want?

A PLL won't fix the clock source's error, but it can make it worse, so you'll need to have a pretty nice PLL, too.  Not one that you'll find in an FPGA.

[Someone]

Sorry, I should have further specified "at high frequency."  To borrow the WSPR example again, the challenge is generating square waves at ~ 10 MHz with a frequency resolution of ~ 1 Hz.  A naive approach based on integer division would require a clock in the terahertz region.  Clearly not an option.

My question really boils down to whether there are approaches which reduce complexity and/or power over the obvious DDS-followed-by-a-comparator.

You need a 10MHz clock and be able to fine tune it down to 1 hz.

So you need a reference clock that is better than 10 part per billion if you want to set your clock to 10,000,001 and have an error of 0.1 hz.  That's oven controlled oscillator territory.

Is this the requirement you need, or the control you want?

A PLL won't fix the clock source's error, but it can make it worse, so you'll need to have a pretty nice PLL, too.  Not one that you'll find in an FPGA.

The OP talks about precision and resolution, not accuracy. Accuracy is easy to provide with a slow servo loop around this much more complicated VCO equivalent.

[Daving]

Need an oven controlled oscillator for that kind of precision, too.  Take a close look at the jitter specs of your room temperature crystals that's your precision.  Now take a look at temperature coefficients and time coefficients, there's your accuracy.

Having precision down to 1 ppb with a precision/accuracy of 20ppm doesn't make sense.

If the OP, doesn't need this level of precision, then the OP should consider relaxing the resolution requirement.  If he needs accuracy and precision implied by his resolution, then the answers provided will only lead the OP to frustration.

Either way, everyone is jumping to provide solutions without defining the requirements.

Anyway, carry on.

[tggzzz]

Having precision down to 1 ppb with a precision/accuracy of 20ppm doesn't make sense.

I worked for a company that sold a cable attenuation meter with 0.001dB resolution and stability, but only a 0.1dB accuracy.

It sold because the customers were interested in changes over time as the cable was heated and cooled. Each temperature test took a week.

[Daving]

I worked for a company that sold a cable attenuation meter with 0.001dB resolution and stability, but only a 0.1dB accuracy.

It sold because the customers were interested in changes over time as the cable was heated and cooled. Each temperature test took a week.

Okay.  To you, measuring is the same thing as generating/sourcing.

There are many reasons why having more resolution than you have either precision or accuracy in measuring is useful.  The time frame for the test gives some indication.
Large amounts of averaging (or filtering in general) can increase the effective number of bits of a measurement.  The rule of thumb is that to double your precision, you need to take four times the measurements.  There are of course exceptions to this.  It is just a rule of thumb, afterall.

The point is, the requirements unusual, and it'll be helpful to clarify them in order to present the correct solution to the OP (or rather avoid giving incorrect solutions).

[mark03]

The point is, the requirements unusual, and it'll be helpful to clarify them in order to present the correct solution to the OP (or rather avoid giving incorrect solutions).

Daving, while it may be advantageous in many digital-comms applications to discipline the oscillator using GPS or another high-accuracy source, I intentionally picked the WSPR example (see above) because there are a variety of very simple homebrew WSPR beacons.  Certainly, the Raspberry Pi beacon has stability and jitter properties far worse than what we have been discussing, yet it works quite well in practice.

BTW there are no firm requirements because this is a spare-time project, an opportunity to learn as I go.  One of the main advantages of a hobby project, IMO, is not having requirements.  I have enough of those at work.  Of course, I wouldn't be pursuing this if not for the obvious existence proofs.

[tggzzz]

I worked for a company that sold a cable attenuation meter with 0.001dB resolution and stability, but only a 0.1dB accuracy.

It sold because the customers were interested in changes over time as the cable was heated and cooled. Each temperature test took a week.

Okay.  To you, measuring is the same thing as generating/sourcing.

Que?

There are many reasons why having more resolution than you have either precision or accuracy in measuring is useful.  The time frame for the test gives some indication.

Sorry, I was too brief. Many measurements were taken over the course of the week as the drum of cable was heated and cooled. The drum just fitted into a test chamber the size of a small room - and had a commensurately long thermal time constant.

They were coaxial submarine cables, typically for transatlantic use; I wish I'd kept a piece of TAT-7.

Large amounts of averaging (or filtering in general) can increase the effective number of bits of a measurement.  The rule of thumb is that to double your precision, you need to take four times the measurements.  There are of course exceptions to this.  It is just a rule of thumb, afterall.

Indeed, but in this case everything was pure analogue with not a computer in sight. It was the 1970s, after all.

[Someone]

Need an oven controlled oscillator for that kind of precision, too.  Take a close look at the jitter specs of your room temperature crystals that's your precision.  Now take a look at temperature coefficients and time coefficients, there's your accuracy.

Having precision down to 1 ppb with a precision/accuracy of 20ppm doesn't make sense.

If the OP, doesn't need this level of precision, then the OP should consider relaxing the resolution requirement.  If he needs accuracy and precision implied by his resolution, then the answers provided will only lead the OP to frustration.

Either way, everyone is jumping to provide solutions without defining the requirements.

Anyway, carry on.

Do read the whole thread, the OP has clarified they are looking for resolution as the primary goal. Multimeters can have a precision of 1 ppm while the accuracy is 100ppm or worse, precision does have importance over accuracy in some applications.

Synthesised VCOs using calibrated rolling delay lines/phase outputs add jitter equal to the largest delay step which is going to be much larger than the jitter of a good oscillator, but can be less than the jitter of a low performance PLL. How much effort and resources are worth spending on this are project dependent, but the example from Xilinx is very cost effective in the applications they targeted.