I would expect data READ FROM a BRAM where you were fail to meet timing to be corrupt, but this seem to be saying that the act of reading the data while failing to meet timing CORRUPTS THE MEMORY CONTENTS, not at all the same thing.
Now managing to trigger this looks like exposing a bug in your HDL, so this sort of fits into the "Doctor it hurts when I do this" category, but even in the presence of such a bug, this would be unexpected behaviour so better it be documented, especially for customers looking to push to ASIC where timings may be slightly different.
Regards, Dan.